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AD9684-500EBZ View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD9684-500EBZ Datasheet PDF : 64 Pages
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AD9684
Product
Overview
Online
Documentation
Design
Resources
Discussion
Sample
& Buy
Data Sheet
Parameter
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tj)
Out of Range Recovery Time
Temperature
Full
Full
Full
Min
Typ
530
55
1
1 The maximum sample rate is the clock rate after the divider.
2 The minimum sample rate operates at 300 MSPS.
3 This specification is valid for parallel interleaved, channel multiplexed, and byte mode output modes.
4 This specification is valid for byte mode output mode only.
5 No DDCs used.
6 Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode.
Max
Unit
ps
fs rms
Clock Cycles
TIMING SPECIFICATIONS
Table 5.
Parameter
CLK± to SYNC± TIMING REQUIREMENTS
tSU_SR
tH_SR
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
See Figure 2
Device clock to SYNC± setup time
Device clock to SYNC± hold time
See Figure 3
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge (not shown in Figure 3)
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in Figure 3)
Timing Diagrams
Min Typ Max Unit
117
ps
−96
ps
2
ns
2
ns
40
ns
2
ns
2
ns
10
ns
10
ns
10
ns
10
ns
CLK–
CLK+
SYNC–
SYNC+
tSU_SR
tH_SR
Figure 2. SYNC± Setup and Hold Timing
tDS
tHIGH
tCLK
tH
tS
tDH
tLOW
CSB
SCLK DON’T CARE
DON’T CARE
SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9
A8
A7
D5
D4
D3
D2
D1
D0 DON’T CARE
Figure 3. Serial Port Interface Timing Diagram
Rev. 0 | Page 8 of 64
 

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