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AD9684 View Datasheet(PDF) - Analog Devices

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Description
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AD9684 Datasheet PDF : 64 Pages
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AD9684
Product
Overview
Online
Documentation
Design
Resources
Discussion
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Data Sheet
Chip
Application
Layer
Four DDCs
Chip
Decimation
Ratio
16
DDC Input
Type
Real
DDC
Output
Type
Complex
Bandwidth
Per DDC1
9.625% × fS
Number of Virtual
Converters
Required (M)
8
Register Settings2
Register 0x200 = 0x03 (four DDCs, I/Q
selected)
Register 0x201 = 0x04 (chip decimate
by 16)
Register 0x310, Register 0x330,
Register 0x350, Register 0x370 = 0x42
(real mixer, 6 dB gain, variable IF,
complex output, HB4 + HB3 + HB2 +
HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input =
ADC Channel A, DDC 0 Q input = ADC
Channel A)
Register 0x331 = 0x00 (DDC 1 I input =
ADC Channel A, DDC 1 Q input = ADC
Channel A)
Register 0x351 = 0x05 (DDC 2 I input =
ADC Channel B, DDC 2 Q input = ADC
Channel B)
Register 0x371 = 0x05 (DDC 3 I input =
ADC Channel B, DDC 3 Q input = ADC
Channel B)
Register 0x314, 0x315, 0x320, 0x321 =
FTW and POW set as required by
application for DDC 0
Register 0x334, Register 0x335,
Register 0x340, Register 0x341 = FTW
and POW set as required by application
for DDC 1
Register 0x354, Register 0x355,
Register 0x360, Register 0x361 = FTW
and POW set as required by application
for DDC 2
Register 0x374, Register 0x375,
Register 0x380, Register 0x381 = FTW
and POW set as required by application
for DDC 3
1 fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop band alias rejection.
2 The NCOs must be synchronized either through the SPI or through the SYNC± pins after all writes to the FTW or POW registers are complete. This ensures the proper
operation of the NCO. See the NCO Synchronization section for more information.
Rev. 0 | Page 46 of 64
 

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