AD9684 View Datasheet(PDF) - Analog Devices

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AD9684

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter

Analog Devices 

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AD9684

For example, if the ADC sampling frequency (fS) is 1250 MSPS

and the carrier frequency (fC) is 416.667 MHz,

NCO _ FTW = round212 mod(416.667,1250)  = 1365 MHz



1250



This, in turn, converts to 0x555 in the 12-bit, twos complement

representation for NCO_FTW. Calculate the actual carrier

frequency based on the following equation:

fC _ ACTUAL

=

NCO _ FTW

212

×

fS

= 416.56

MHz

A 12-bit POW is available for each NCO to create a known

phase relationship between multiple AD9684 chips or

individual DDC channels inside one AD9684 chip.

The following procedure must be followed to update the FTW

and/or POW registers to ensure proper operation of the NCO:

1. Write to the FTW registers for all the DDCs.

2. Write to the POW registers for all the DDCs.

3. Synchronize the NCOs either through the DDC soft reset bit,

accessible through the SPI, or through the assertion of the

SYNC± pins.

Note that the NCOs must be synchronized either through the

SPI or through the SYNC± pins after all writes to the FTW or

POW registers are complete. This synchronization is necessary

to ensure the proper operation of the NCO.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW)

that determines the instantaneous phase of the NCO. The initial

reset value of each PAW is determined by the POW, described

in the Setting Up the NCO FTW and POW section. The phase

increment value of each PAW is determined by the FTW.

Use the following two methods to synchronize multiple PAWs

within the chip:

• Using the SPI. Use the DDC NCO soft reset bit in the DDC

synchronization control register (Register 0x300, Bit 4) to

reset all the PAWs in the chip. This is accomplished by

toggling the DDC NCO soft reset bit. Note that this

method synchronizes DDC channels within the same

AD9684 chip only.

• Using the SYNC± pins. When the SYNC± pins are enabled

in the SYNC± control registers (Register 0x120 and

Register 0x121), and the DDC synchronization is enabled

in Bits[1:0] in the DDC synchronization control register

(Register 0x300), any subsequent SYNC± event resets all

the PAWs in the chip. Note that this method synchronizes

DDC channels within the same AD9684 chip or DDC

channels within separate AD9684 chips.

Mixer

The NCO is accompanied by a mixer, which operates similarly

to an analog quadrature mixer. It performs the downconversion

of input signals (real or complex) by using the NCO frequency

as a local oscillator. For real input signals, this mixer performs a

real mixer operation with two multipliers. For complex input

signals, the mixer performs a complex mixer operation with

four multipliers and two adders. The mixer adjusts its operation

based on the input signal (real or complex) provided to each

individual channel. The selection of real or complex inputs can be

controlled individually for each DDC block using Bit 7 of the DDC

control registers (Register 0x310, Register 0x330, Register 0x350,

and Register 0x370).

Rev. 0 | Page 39 of 64

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