AD9684 View Datasheet(PDF) - Analog Devices

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AD9684

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter

Analog Devices 

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AD9684

Real (I) Output (Complex to Real Enabled)

HB2 FIR +

HB1 FIR

(DCM1 = 2)

HB3 FIR +

HB2 FIR +

HB1 FIR

(DCM1 = 4)

HB4 FIR +

HB3 FIR +

HB2 FIR +

HB1 FIR

(DCM1 = 8)

N + 10

N+4

N+2

N + 11

N+5

N+3

N + 12

N+6

N+2

N + 13

N+7

N+3

N + 14

N+6

N+2

N + 15

N+7

N+3

1 DCM means decimation.

HB1 FIR

(DCM1 = 2)

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

Complex (I/Q) Outputs (Complex to Real Disabled)

HB2 FIR +

HB1 FIR

(DCM1 = 4)

HB3 FIR +

HB2 FIR +

HB1 FIR

(DCM1 = 8)

HB4 FIR +

HB3 FIR +

HB2 FIR +

HB1 FIR

(DCM1 = 16)

N+4

N+2

N

N+5

N+3

N+1

N+6

N+2

N

N+7

N+3

N+1

N+6

N+2

N

N+7

N+3

N+1

Table 12. DDC Samples When the Chip Decimation Ratio = 4

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB3 FIR + HB2 FIR + HB1

FIR (DCM1 = 4)

HB4 FIR + HB3 FIR + HB2 FIR HB2 FIR + HB1 FIR

+ HB1 FIR (DCM1 = 8)

(DCM1 = 4)

HB3 FIR + HB2 FIR +

HB1 FIR (DCM1 = 8)

HB4 FIR + HB3 FIR + HB2 FIR

+ HB1 FIR (DCM1 = 16)

N

N

N

N

N

N+1

N+1

N+1

N+1

N+1

N+2

N

N+2

N

N

N+3

N+1

N+3

N+1

N+1

N+4

N+2

N+4

N+2

N

N+5

N+3

N+5

N+3

N+1

N+6

N+2

N+6

N+2

N

N+7

N+3

N+7

N+3

N+1

1 DCM means decimation.

Table 13. DDC Samples When the Chip Decimation Ratio = 8

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8)

HB3 FIR + HB2 FIR + HB1 FIR(DCM1 = 8)

HB4 FIR + HB3 FIR + HB2 FIR + HB1

FIR (DCM1 = 16)

N

N

N

N+1

N+1

N+1

N+2

N+2

N

N+3

N+3

N+1

N+4

N+4

N+2

N+5

N+5

N+3

N+6

N+6

N+2

N+7

N+7

N+3

1 DCM means decimation.

Table 14. DDC Samples When the Chip Decimation Ratio = 16

Real (I) Output (Complex to Real Enabled)

HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)

Not applicable

Not applicable

Not applicable

Not applicable

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)

N

N+1

N+2

N+3

1 DCM means decimation.

Rev. 0 | Page 35 of 64

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