AD9684 View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

AD9684

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter

Analog Devices 

AD9684

Product

Overview

Pin No.

Analog

E14, F14

E1, F1

H10

A7, A8

CMOS Outputs

J14, J1

Digital Inputs

C7, C8

Data Outputs

N6, P6

M1, M2

N1, P1

N2, P2

N3, P3

N4, P4

N5, P5

N9, P9

N10, P10

N11, P11

N12, P12

N13, P13

N14, P14

M13, M14

L13, L14

K13, K14

SPI Controls

K4

J4

H4

J13

Online

Documentation

Design

Resources

Discussion

Sample

& Buy

Data Sheet

Mnemonic

Type

Description

VIN−A, VIN+A

VIN−B, VIN+B

V_1P0

CLK+, CLK−

Input

Input

Input/DNC

Input

ADC A Analog Input Complement/True.

ADC B Analog Input Complement/True.

1.0 V Reference Voltage Input/Do Not Connect. This pin is

configurable through the SPI as a no connect or as an input.

Do not connect this pin if using the internal reference. This pin

requires a 1.0 V reference voltage input if using an external

voltage reference source.

Clock Input True/Complement.

FD_A, FD_B

Output

Fast Detect Outputs for Channel A and Channel B.

SYNC+, SYNC−

Input

Active High LVDS SYNC Input—True/Complement.

D0−, D0+

D1+, D1−

D2−, D2+

D3−, D3+

D4−, D4+

D5−, D5+

D6−, D6+

D7−, D7+

D8−, D8+

D9−, D9+

D10−, D10+

D11−, D11+

D12−, D12+

D13−, D13+

STATUS−, STATUS+

DCO−, DCO+

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

LVDS Lane 0 Output Data—Complement/True.

LVDS Lane 1 Output Data—True/Complement.

LVDS Lane 2 Output Data—Complement/True.

LVDS Lane 3 Output Data—Complement/True.

LVDS Lane 4 Output Data—Complement/True.

LVDS Lane 5 Output Data—Complement/True.

LVDS Lane 6 Output Data—Complement/True.

LVDS Lane 7 Output Data—Complement/True.

LVDS Lane 8 Output Data—Complement/True.

LVDS Lane 9 Output Data—Complement/True.

LVDS Lane 10 Output Data—Complement/True.

LVDS Lane 11 Output Data—Complement/True.

LVDS Lane 12 Output Data—Complement/True.

LVDS Lane 13 Output Data—Complement/True.

LVDS Status Output Data—Complement/True.

LVDS Digital Clock Output Data—Complement/True.

SDIO

SCLK

CSB

PDWN/STBY

Input/output

Input

Input

Input

SPI Serial Data Input/Output.

SPI Serial Clock.

SPI Chip Select (Active Low).

Power-Down Input (Active High). The operation of this pin

depends on the SPI mode and can be configured as power-

down or standby.

Rev. 0 | Page 18 of 64

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