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BR34L02FV-W View Datasheet(PDF) - ROHM Semiconductor

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BR34L02FV-W Datasheet PDF : 25 Pages
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BR34L02FV-W
zApplication
1) WP effective timing
WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to
WP effective timingas follows.
During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective
period.
The period from the start condition to the rising edge of the clock which take in D0 of the data (the first byte of the data
for Page Write) is the cancellation invalid period. WP input is don’t care during the period. Setup time for rising edge of
the SCL which takes in D0 must be more than 100ns.
The period from the rising edge of SCL which takes in D0 to the end of internal write cycle (tWR) is the cancellation
effective period. In case of setting WP to “H” during tWR, WRITE operation is stopped in the middle and the data of
accessing address is not guaranteed, so that write correct data again please.
It is not necessary waiting tWR (5msmax.) after stopping command by WP, because the device is stand by state.
· The rising edge of the clock
which take in D0
SCL
SDA
D1 D0 ACK
AN ENLARGEMENT
SCL
SDA D0
ACK
· The rising edge
of SDA
AN ENLARGEMENT
SDA
S
T
A
R
T
SLAVE
ADDRESS
A
C
K
L
WORD
ADDRESS
A
C
K
L
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
L
DATA
AA
CC
KK
LL
S
T
O
P
tWR
WP cancellation invalid period
WP cancellation effective period
Stop of the write
operation
WP
Data is not
No data will be written
guaranteed
Fig.18 WP EFFECTIVE TIMING
Rev.A 13/24
 

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