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MC14011UBD View Datasheet(PDF) - Motorola => Freescale

Part NameDescriptionManufacturer
MC14011UBD UB-Suffix Series CMOS Gates Motorola
Motorola => Freescale Motorola
MC14011UBD Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
UB-Suffix Series CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
non–buffered functions.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
Devices
LOGIC DIAGRAMS
MC14001UB
Quad 2–Input
NOR Gate
1
2
3
5
4
6
8
10
9
12
11
13
MC14012UB
Dual 4–Input
NAND Gate
2
3
1
4
5
9
10
13
11
12
NC = 6, 8
MC14002UB
Dual 4–Input
NOR Gate
2
3
4
1
5
9
10
13
11
12
NC = 6, 8
MC14011UB
Quad 2–Input
NAND Gate
1
3
2
5
4
6
8
10
9
12
11
13
MC14023UB
Triple 3–Input
NAND Gate
1
2
9
8
3
4
6
5
11
12
10
13
MC14025UB
Triple 3–Input
NOR Gate
1
2
9
8
3
4
6
5
11
12
10
13
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
MC14001UB
Quad 2-Input NOR Gate
MC14002UB
Dual 4-Input NOR Gate
MC14011UB
Quad 2-Input NAND Gate
MC14012UB
Dual 4-Input NAND Gate
MC14023UB
Triple 3-Input NAND Gate
MC14025UB
Triple 3-Input NOR Gate
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v v operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
REV 3
1/94
©MMCot1or4o0la0, I1nUc.B1995
18
MOTOROLA CMOS LOGIC DATA
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