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ISL28023 View Datasheet(PDF) - Intersil

Part Name
Description
MFG CO.
ISL28023 Datasheet PDF : 55 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin Configuration
ISL28023
ISL28023
(24 LD QFN)
TOP VIEW
24 23 22 21 20 19
NC 1
18 VCC
GND 2
17 I2CVCC
AUXP 3
AUXM 4
GND
16 A2
15 A1
AUXV 5
14 A0
DAC_OUT 6
13 GND
7 8 9 10 11 12
Pin Descriptions
PIN NUMBER PIN NAME
TYPE/DIR
PIN DEFINITION
1, 9, 20
NC
N/A
No connect
2
GND
Power
Ground
3
AUXP
Analog Input Auxiliary port differential input (plus)
4
AUXM
Analog Input Auxiliary port differential input (minus)
5
AUXV
Analog Input Auxiliary port single ended input
6
DAC_OUT
Analog Output DAC voltage output
7
SMBCLK
Digital Input SMBus/I2C clock input
8
SMBDAT Digital Input/Output SMBus/I2C data
10
SMBALERT1 Digital Output SMBus Alert1, open-drain output
11
SMBALERT2 Digital Output CPU interrupt signal: It is used as CPU interrupt signal
12
EXT_CLK
Digital Input External ADC clock input
13
GND
Power
Ground
14
A0
Digital Input SMBus/I2C address input
15
A1
Digital Input SMBus/I2C address input
16
A2
Digital Input SMBus/I2C address input
17
I2CVCC
Power
I2C level shifter power supply. This pin should be connected to VCC pin if level shifter is not used.
18
VCC
Power
Chip power supply
19
VREG_OUT
Power
Voltage regulator output, proper decoupling capacitor should be connected to this pin
21
VINM
Analog Input Current sense minus input
22
VINP
Analog Input Current sense plus input
23
VREG_IN
Power
Voltage regulator input. This pin should be connected to ground in case voltage regulator is not used.
24
VBUS
Power
VBUS voltage sense
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4
FN8389.4
June 17, 2015
 

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