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ISL28023FR12Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL28023FR12Z Precision Digital Power Monitor with Margining / 24 Ld QFN Package Intersil
Intersil Intersil
ISL28023FR12Z Datasheet PDF : 55 Pages
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ISL28023
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP-VINM = 80mV, AUXP-AUXM = 80mV, AuxV = 3V,
Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. (Continued)
PARAMETER
CPIN
fSMBCLK
tIN
DESCRIPTION
SMBDAT and SMBCLK Pin Capacitance
SMBCLK Frequency
TEST CONDITIONS
TA = +25°C, f = 1MHz, I2CVCC = 5V,
VIN = 0V, VOUT = 0V
Pulse Width Suppression Time at SMBDAT Any pulse narrower than the max spec
and SMBCLK Inputs
is suppressed
MIN
(Note 6)
MAX
TYP (Note 6) UNIT
10
pF
400
kHz
50
ns
tAA
tBUF
tLOW
tHIGH
SMBCLK Falling Edge to SMBDAT Output SMBCLK falling edge crossing 30% of
Data Valid
I2CVCC, until SMBDAT exits the 30% to
70% of I2CVCC window
Time the Bus Must be Free Before the Start SMBDAT crossing 70% of I2CVCC during
of a New Transmission
a STOP condition, to SMBDAT crossing
70% of I2CVCC during the following
START condition
Clock LOW Time
Measured at the 30% of I2CVCC
crossing
Clock HIGH Time
Measured at the 70% of I2CVCC
crossing
1300
1300
600
900
ns
ns
ns
ns
tSU:STA
START Condition Setup Time
SMBCLK rising edge to SMBDAT falling
600
edge. Both crossing 70% of I2CVCC
ns
tHD:STA
START Condition Hold Time
From SMBDAT falling edge crossing
600
ns
30% of I2CVCC to SMBCLK falling edge
crossing 70% of I2CVCC
tSU:DAT
Input Data Setup Time
From SMBDAT exiting the 30% to 70%
100
ns
of VCC window, to SMBCLK rising edge
crossing 30% of I2CVCC
tHD:DAT
Input Data Hold Time
From SMBCLK falling edge crossing
20
30% of I2CVCC to SMBDAT entering the
30% to 70% of I2CVCC window
900
ns
tSU:STO
STOP Condition Setup Time
From SMBCLK rising edge crossing 70%
600
ns
of I2CVCC, to SMBDAT rising edge
crossing 30% of I2CVCC
tHD:STO
STOP Condition Hold Time
From SMBDAT rising edge to SMBCLK
600
ns
falling edge. Both crossing 70% of
I2CVCC
tDH
Output Data Hold Time
From SMBCLK falling edge crossing
0
30% of I2CVCC, until SMBDAT enters
the 30% to 70% of I2CVCC window
tR
SMBDAT and SMBCLK Rise Time
From 30% to 70% of I2CVCC
tF
SMBDAT and SMBCLK Fall Time
From 70% to 30% of I2CVCC
20 + 0.1 x Cb
20 + 0.1 x Cb
Cb
Capacitive Loading of SMBDAT or SMBCLK Total on-chip and off-chip
10
ns
300
ns
300
ns
400
pF
RPU
SMBDAT and SMBCLK Bus Pull-up Resistor Maximum is determined by tR and tF
1
kΩ
Off-chip
For Cb = 400pF, max is about
2kΩ~2.5kΩ
For Cb = 40pF, max is about
15kΩ~20kΩ
POWER SUPPLY
Vvcc
Vi2cvcc
Power Supply Voltage at VCC
Power Supply Voltage at I2CVCC
f = DC to 400kHz
3.0
3.3
5.5
V
1.2
3.3
5.5
V
Only ADC in Conversion Mode
All other blocks are disabled
690
830
µA
Submit Document Feedback 10
FN8389.4
June 17, 2015
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