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UPD780982 View Datasheet(PDF) - NEC => Renesas Technology

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UPD780982
NEC
NEC => Renesas Technology NEC
UPD780982 Datasheet PDF : 115 Pages
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CHAPTER 3 CONTROL
3.6.4 INTP0 safety stop processing
Processing starts at the falling edge of the external interrupt input to the INTP0 input pin.
To prevent the occurrence of a safety stop that is caused by noise, INTP0 pin sampling is repeated during
interrupt processing. Stop setting processing is performed only when two consecutive reads of the active (low) level
give the same value.
Figure 3-12. Safety Stop Conditions
40 µs min. (IGBT specification)
Error signal
Input Input
7 µs
During stop setting, output of the 10-bit inverter control timer (TM7) is prohibited and target frequency RFOUT is
set to the stop setting (0FFH).
During main processing, when the target frequency is set to the stop setting, the main mode is also set to the stop
setting. Also, timing set interrupt is prohibited.
3.6.5 Dead time input
During other than PWM output processing, to measure the dead time of the CPU, test pin (P66, P67) output is
performed.
Test pin output consists of the processing shown below.
(1) Inverter output setting (subroutine: INVSET)
P67 is set immediately before the subroutine call of the main loop.
P67 is reset immediately after the subroutine call of the main loop.
(2) INTTM7 interrupt processing
At the beginning of interrupt processing, P66 is set.
After the completion of interrupt processing, P66 is restored.
Application Note U13119EJ4V0AN
45
 

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