LA1862M View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

View to exact match

LA1862M

Single-chip Tuner System for Car Stereo

SANYO -> Panasonic 

LA1862M

4. The following figure illustrates one possible circuit design using both the IF count buffer and the SD output circuit.

Apply 5 V for seek

SD output

IF count buffer output

Noise Canceller Block

1. The resistor and capacitor connected to pin 6 determine

the noise canceller sensitivity.

2. The resistor and capacitor connected to pin 7 determine

the noise AGC.

3. Pin 9 is the gate trigger output. The resistor and capacitor

connected to pin 9 determine the length of time that the

gate is open.

4. The resistor and capacitor connected to pins 10 and 11 are

for holding the input signal level when the noise canceller

gate operates. The storage time depends on the time that

the gate is open. The time constant for the RC circuit on

pins 10 and 11 must, therefore, be such that the output

retention signal level does not drop during this interval.

Noise canceller input waveform

Noise canceller output waveform

Output retention

(storage)

5. Pin 26 is the noise canceller input. An appropriate input level is 250 mVrms for 100% dev and fm = 1 kHz. Excessive input

can exceed the noise canceller dynamic range, increasing the THD. Insufficient input, on the other hand, lowers the

signal-to-noise ratio and reduces pilot lamp sensitivity.

No. 4092- 15/27

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