ST10F276R-6QR3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

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ST10F276R-6QR3

16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM

STMicroelectronics 

ST10F276E

Internal Flash memory

4.4.6

Flash non-volatile access protection register 0

Due to ST10 architecture, the XFLASH is seen as external memory: this made impossible to

access protect it from real external memory or internal RAM.

FNVAPR0 (0x0E DFB8)

NVR

Delivery value: ACFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

DBGP ACCP

RW RW

Table 23.

Bit

ACCP

DBGP

Flash non-volatile access protection register 0

Function

Access Protection

This bit, if programmed at 0, disables any access (read/write) to data mapped inside

IFlash Module address space, unless the current instruction is fetched from one of the

two Flash modules.

Debug Protection

This bit, if erased at 1, allows to by-pass all the protections using the Debug features

through the Test Interface. If programmed at 0, on the contrary, all the debug features,

the Test Interface and all the Flash Test Modes are disabled. Even STMicroelectronics

will not be able to access the device to run any eventual failure analysis.

4.4.7

Flash non-volatile access protection register 1 low

FNVAPR1L (0x0E DFBC)

NVR

Delivery value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 24. Flash non-volatile access protection register 1 low

Bit

Function

PDS(15:0)

Protections Disable 15-0

If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP is

disabled. Bit PDS0 can be programmed at 0 only if bits DBGP and ACCP have already

been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has

already been programmed at 0.

Doc ID 12303 Rev 3

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