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ST10F276S-4T3 View Datasheet(PDF) - STMicroelectronics

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ST10F276S-4T3 Datasheet PDF : 235 Pages
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Internal Flash memory
ST10F276E
Table 17. Flash error register (continued)
Bit
Function
SEQER
Sequence error
This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L,
FDR1H/L-FDR0H/L) are not correctly filled to execute a valid write operation. in this
case no write operation is executed. This bit has to be software reset.
RESER
WPF
Resume error
This bit is automatically set when a suspended program or erase operation is not
resumed correctly due to a protocol error. In this case the suspended operation is
aborted. This bit has to be software reset.
Write protection flag
This bit is automatically set when trying to program or erase in a sector write
protected. In case of multiple sector erase, the not protected sectors are erased, while
the protected sectors are not erased and bit WPF is set. This bit has to be software
reset.
4.3.12
XFlash interface control register
This register is used to configure the XFLASH interface behavior on the XBUS. It allows to
set the number of wait states introduced on the XBUS before the internal READY signal is
given to the ST10 bus master.
XFICR (0xE E000h)
XBUS
Reset value: 000Fh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
WS3 WS2 WS1 WS0
RW RW RW RW
Table 18. X-Flash interface control register
Bit
Function
WS(3:0)
Wait state setting
These three bits are the binary coding of the number of wait states introduced by the
XFLASH interface through the XBUS internal READY signal. Default value after reset
is 1111, that is the up to 15 wait states are set. The following recommendations for the
ST10F276E are hereafter reported:
For fCPU > 40MHz1 Wait-StateWS(3:0) = ‘0001’
For fCPU 40MHz0 Wait-StateWS(3:0) = ‘0000’
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Doc ID 12303 Rev 3
 

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