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LC4256ZE-7TN48CES View Datasheet(PDF) - Lattice Semiconductor

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LC4256ZE-7TN48CES
Lattice
Lattice Semiconductor Lattice
LC4256ZE-7TN48CES Datasheet PDF : 54 Pages
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Table 4. Product Term Expansion Capability
Expansion
Chains
Chain-0
Chain-1
Chain-2
Chain-3
Macrocells Associated with Expansion Chain
(with Wrap Around)
M0 M4 M8 M12 M0
M1 M5 M9 M13 M1
M2 M6 M10 M14 M2
M3 M7 M11 M15 M3
Max PT/
Macrocell
75
80
75
70
Every time the super cluster allocator is used, there is an incremental delay of tEXP. When the super cluster alloca-
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Power-up
Initialization
Shared PT Initialization
PT Initialization (optional)
PT Initialization/CE (optional)
From Logic Allocator
Delay
RP
D/T/L Q
From I/O Cell
To ORP
To GRP
CE
Single PT
Block CLK0
Block CLK1
Block CLK2
Block CLK3
PT Clock (optional)
Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
• Block CLK0
• Block CLK1
6
 

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