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LC4256ZE-7MN48I View Datasheet(PDF) - Lattice Semiconductor

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Description
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LC4256ZE-7MN48I
Lattice
Lattice Semiconductor Lattice
LC4256ZE-7MN48I Datasheet PDF : 54 Pages
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Lattice Semiconductor
Figure 3. AND Array
In[0]
In[34]
In[35]
ispMACH 4000ZE Family Data Sheet
PT0
PT1
PT2 Cluster 0
PT3
PT4
Note:
Indicates programmable fuse.
PT75
PT76
PT77
PT78
PT79
Cluster 15
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE/BIE
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000ZE family is 4+1 (total 5) product
terms. The software automatically considers the availability and distribution of product term clusters as it fits the
functions within a GLB. The logic allocator is designed to provide two speed paths: 20-PT Speed Locking path and
an up to 80-PT path. The availability of these two paths lets designers trade timing variability for increased perfor-
mance.
The enhanced Logic Allocator of the ispMACH 4000ZE family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
to to
n-1 n-2
from from
n-1 n-4
n
Cluster
Individual Product
Term Allocator
5-PT
From
n-4
1-80
PTs
To XOR (MC)
to
from from
n+1
n+2 n+1
Cluster
Allocator
4
To n+4
SuperWIDE™
Steering Logic
 

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