datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

LC4256ZE-7MN64CES View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
View to exact match
LC4256ZE-7MN64CES
Lattice
Lattice Semiconductor Lattice
LC4256ZE-7MN64CES Datasheet PDF : 54 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ispMACH® 4000ZE Family
August 2008
1.8V In-System Programmable
Ultra Low Power PLDs
Data Sheet DS1022
Features
High Performance
• fMAX = 260MHz maximum operating frequency
• tPD = 4.4ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Ease of Design
• Flexible CPLD macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
Ultra Low Power
• Standby current as low as 10µA typical
• 1.8V core; low dynamic power
• Operational down to 1.6V VCC
• Superior solution for power sensitive consumer
applications
• Per pin pull-up, pull-down or bus keeper
control*
Power Guard with multiple enable signals*
Broad Device Offering
• 32 to 256 macrocells
• Multiple temperature range support
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
• Space-saving packages
Easy System Integration
• Operation with 3.3V, 2.5V, 1.8V or 1.5V
LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing support
• Open-drain output option
• Programmable output slew rate
• 3.3V PCI compatible
• I/O pins with fast setup path
Input hysteresis*
• 1.8V core power supply
• IEEE 1149.1 boundary scan testable
• IEEE 1532 ISC compliant
• 1.8V In-System Programmable (ISP™) using
Boundary Scan Test Access Port (TAP)
• Pb-free package options (only)
On-chip user oscillator and timer*
*New enhanced features over original ispMACH 4000Z
Table 1. ispMACH 4000ZE Family Selection Guide
ispMACH 4032ZE
Macrocells
32
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltages (V)
4.4
2.2
3.0
260
1.8V
Packages1 (I/O + Dedicated Inputs)
48-Pin TQFP (7 x 7mm)
32+4
64-Ball csBGA (5 x 5mm)
32+4
100-Pin TQFP (14 x 14mm)
144-Pin TQFP (20 x 20mm)
144-Ball csBGA (7 x 7mm)
1. Pb-free only.
ispMACH 4064ZE
64
4.7
2.5
3.2
241
1.8V
32+4
48+4
64+10
64+10
ispMACH 4128ZE
128
5.8
2.9
3.8
200
1.8V
64+10
96+4
96+4
ispMACH 4256ZE
256
5.8
2.9
3.8
200
1.8V
64+10
96+14
108+4
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1022_01.2
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]