LC4256ZE-7TN100IES View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

View to exact match

LC4256ZE-7TN100IES

1.8V In-System Programmable Ultra Low Power PLDs

Lattice Semiconductor 

Lattice Semiconductor

Figure 8. I/O Cell

GOE 0

GOE 1

GOE 2

GOE 3

From ORP

VCC

ispMACH 4000ZE Family Data Sheet

I/O Bus Maintenance

VVCCCCOO

From ORP

Power Guard

0

To Macrocell

1

To GRP

Block Input Enable (BIE)

(From Block PT)

Power Guard Disable Fuse (PGDF)

Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can

also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-

pendent of the VCCO supplied to its I/O bank. The I/O standards supported are:

• LVTTL

• LVCMOS 3.3

• LVCMOS 2.5

• LVCMOS 1.8

• LVCMOS 1.5

• 3.3V PCI Compatible

All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down

resistor selectable on a “per-pin” basis. A fourth option is to provide none of these. The default in both hardware

and software is such that when the device is erased or if the user does not specify, the input structure is configured

to be a Pull-down Resistor.

Each ispMACH 4000ZE device I/O has an individually programmable output slew rate control bit. Each output can

be individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew

setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer

reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated

lines, the fast slew rate can be used to achieve the highest speed.

The ispMACH 4000ZE family has an always on, 200mV typical hysteresis for each input operational at 3.3V and

2.5V. This provides improved noise immunity for slow transitioning signals.

Power Guard

Power Guard allows easier achievement of standby current in the system. As shown in Figure 9, this feature con-

sists of an enabling multiplexer between an I/O pin and input buffer, and its associated circuitry inside the device.

If the enable signal (E) is held low, all inputs (D) can be optionally isolated (guarded), such that, if any of these were

toggled, it would not cause any toggle on internal pins (Q), thus, a toggling I/O pin will not cause any internal

dynamic power consumption.

10

Share Link: