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DS2482X-101-U View Datasheet(PDF) - Maxim Integrated

Part Name
Description
View to exact match
DS2482X-101-U
MaximIC
Maxim Integrated MaximIC
DS2482X-101-U Datasheet PDF : 24 Pages
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Single-Channel 1-Wire Master with Sleep Mode
Pin Description
PIN NAME
FUNCTION
A1
PCTLZ
Active-Low Control Output for an External p-Channel MOSFET. Provides extra power to the 1-Wire line, e.g.,
for use with 1-Wire devices that require a higher current temporarily to operate.
A2
SLPZ Active-Low Control Input to Activate Low-Power Sleep Mode. This pin should be driven by a push-pull port.
A3
AD0 I2C Address Input. Must be connected to VCC or GND.
B1
SCL I2C Serial Clock Input. Must be connected to VCC through a pullup resistor.
B2
SDA I2C Serial Data Input/Output. Must be connected to VCC through a pullup resistor.
B3
VCC Power-Supply Input
C2
GND Ground Reference
C3
IO Input/Output Driver for 1-Wire Line
CONFIGURATION
REGISTER
T-TIME OSC
SDA
I2C
INPUT/OUTPUT
CONTROLLER
LINE
XCVR
IO
INTERFACE
SCL
CONTROLLER
PCTLZ
AD0
STATUS
REGISTER
SLPZ
READ DATA
DS2482-101
REGISTER
Figure 1. Block Diagram
Detailed Description
The DS2482-101 is a self-timed 1-Wire master that sup-
ports advanced 1-Wire waveform features including
standard and overdrive speeds, active pullup, and
strong pullup for power delivery. The active pullup
affects rising edges on the 1-Wire side. The strong
pullup function uses the same pullup transistor as the
active pullup, but with a different control algorithm. In
addition, the strong pullup activates the PCTLZ pin,
controlling optional external circuitry to deliver addition-
al power beyond the capabilities of the on-chip pullup
transistor. Once supplied with command and data, the
input/output controller of the DS2482-101 performs
time-critical 1-Wire communication functions such as
reset/presence-detect cycle, read-byte, write-byte, sin-
gle-bit R/W, and triplet for ROM Search, without requir-
ing interaction with the host processor. The host obtains
feedback (completion of a 1-Wire function, presence
pulse, 1-Wire short, search direction taken) through the
Status Register and data through the Read Data
Register. The DS2482-101 communicates with a host
processor through its I2C bus interface in standard
mode or in fast mode. The logic state of the address
pin determines the I2C slave address of the
DS2482-101, allowing two devices operating on the
same bus segment without requiring a hub. See
Figure 1 for a block diagram.
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