Philips Semiconductors
TV signal processor-Teletext decoder with
embedded µ-Controller
Tentative Device Specification
TDA935X/6X/8X PS/N2 series
MEMORY INTERFACE
The memory interface controls the access to the
embedded DRAM, refreshing of the DRAM and page
clearing. The DRAM is shared between Data Capture,
Display and Microcontroller sections. The Data Capture
section uses the DRAM to store acquired information that
has been requested. The Display reads the DRAM
information and converts it to RGB output values. The
Microcontroller uses the DRAM as embedded auxiliary
RAM.
DATA CAPTURE
The Data Capture section takes in the analogue
Composite Video and Blanking Signal (CVBS) from One
Chip, and from this extracts the required data, which is
then decoded and stored in SFR memory.
The extraction of the data is performed in the digital
domain. The first stage is to convert the analogue CVBS
signal into a digital form. This is done using an ADC
sampling at 12MHz. The data and clock recovery is then
performed by a Multi-Rate Video Input Processor
(MulVIP). From the recovered data and clock the following
data types are extracted WST Teletext (625/525),Closed
Caption, VPS, WSS. The extracted data is stored in either
memory (DRAM) via the Memory Interface or in SFR
locations.
Data Capture Features
• Video Signal Quality detector.
• Data Capture for 625 line WST
• Data Capture for 525 line WST
• Data Capture for US Closed Caption
• Data Capture for VPS data (PDC system A)
• Data Capture for Wide Screen Signalling (WSS) bit
decoding
• Automatic selection between 525 WST/625WST
• Automatic selection between 625WST/VPS on line 16 of
VBI
• Real-time capture and decoding for WST Teletext in
Hardware, to enable optimised microprocessor
throughput
• Up to 10 pages stored On-Chip
• Inventory of transmitted Teletext pages stored in the
Transmitted Page Table (TPT) and Subtitle Page Table
(SPT)
• Automatic detection of FASTEXT transmission
• Real-time packet 26 engine in Hardware for processing
accented, G2 and G3 characters
• Signal quality detector for WST/VPS data types
• Comprehensive Teletext language coverage
• Full Field and Vertical Blanking Interval (VBI) data
capture of WST data
Analogue to Digital Converter
The CVBS input is passed through a differential to single
ended converter (DIVIS), although in this device it is used
in single ended configuration with a reference.The
analogue output of DIVIS is converted into a digital
representation by a full flash ADC with a sampling rate of
12MHz.
Multi Rate Video Input Processor
The multi rate video input processor is a Digital Signal
Processor designed to extract the data and recover the
clock from the digital CVBS signal.
2001 Jan 18
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