TDA9351PS/N2 View Datasheet(PDF) - Philips Electronics
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TDA9351PS/N2 Datasheet PDF : 118 Pages
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Philips Semiconductors
TV signal processor-Teletext decoder with
embedded µ-Controller
Tentative Device Specification
TDA935X/6X/8X PS/N2 series
5. Enable INT1 using the IE SFR.
6. Enter Power-Down/Idle. Upon wake-up the SAD
should be restored to its conventional operating mode
by disabling the ’DC_COMP’ control bit.
I2C Serial I/O Bus
The I2C bus consists of a serial data line (SDA) and a serial
clock line (SCL). The definition of the I2C protocol can be
found in the 80C51 based 8-bit micro-controllers - Philips
Semiconductors (ref. IC20).
The device operates in four modes: -
• Master Transmitter
• Master Receiver
• Slave Transmitter
• Slave Receiver
The micro-controller peripheral is controlled by the Serial
Control SFR (S1CON) and its Status is indicated by the
status SFR (S1STA). Information is transmitted/received
to/from the I2C bus using the Data SFR (S1DAT) and the
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
The byte level I2C serial port is identical to the I2C serial
port on the 8xC558, except for the clock rate selection bits
CR<2:0>. The operation of the subsystem is described in
detail in the 8xC558 data sheet and can be found in the
80C51 based 8-bit micro-controllers - Philips
Semiconductors (ref. IC20).
Three different IIC selection tables for CR<2:0> can be
configured using the ROMBANK SFR (IIC_LUT<1:0>) as
follows: -
‘558 nominal mode’ (iic_lut=”00”)
This option accommodates the 558 I2C. The various serial
rates are shown below: -
CR2 CR1 CR0
0
0
0
fclk (6MHz)
divided by
60
I2C Bit Frequency
(KHz) at fclk
100
0
0
1
1600
3.75
0
1
0
40
150
0
1
1
30
200
1
0
0
240
25
1
0
1
3200
1.875
1
1
0
160
37.5
1
1
1
120
50
Table 7 IIC Serial Rates ‘558 nominal mode’
‘558 fast mode’ (iic_lut=”01”)
This option accommodates the 558 I2C doubled rates as
shown below: -
CR2 CR1 CR0
0
0
0
fclk (6MHz)
divided by
30
I2C Bit Frequency
(KHz) at fclk
200
0
0
1
800
7.5
0
1
0
20
300
0
1
1
15
400
1
0
0
120
50
1
0
1
1600
3.75
1
1
0
80
75
1
1
1
60
100
Table 8 IIC Serial Rates ‘558 fast mode’
‘558 slow mode’ (iic_lut=”10”)
This option accommodates the 558 I2C rates divided by 2
as shown below: -
CR2 CR1 CR0
0
0
0
fclk (6MHz)
divided by
120
I2C Bit Frequency
(KHz) at fclk
50
0
0
1
3200
1.875
0
1
0
80
75
0
1
1
60
100
1
0
0
480
12.5
1
0
1
6400
0.9375
1
1
0
320
18.75
1
1
1
240
25
Table 9 IIC Serial Rates ‘558 slow mode’
Note: In the above tables the fclk relates to the clock rate of
the 80c51 IIC module (6MHz).
I2C Port Enable
One external I2C port is available. This port is enabled
using TXT21.I2C PORT0. Any information transmitted to
the device can only be acted upon if the port is enabled.
Internal communication between the 80c51
micro-controller and the TV Signal Processor will continue
regardless of the value written to TXT21.I2C PORT0.
LED Support
Port pins P0.5 and P0.6 have a 8mA current sinking
capability to enable LEDs in series with current limiting
resistors to be driven directly, without the need for
additional buffering circuitry.
2001 Jan 18
35
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