TDA9351PS/N2 View Datasheet(PDF) - Philips Electronics

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TDA9351PS/N2

TV signal processor-Teletext decoder with embedded micro-Controller

Philips Electronics 

Philips Semiconductors

TV signal processor-Teletext decoder with

embedded µ-Controller

Tentative Device Specification

TDA935X/6X/8X PS/N2 series

Gat C/T M1 M0 Gat C/T M1 M0

Timer 1

Timer 0

Gate

C/T

Gating control when set. Timer/counter is enabled only

while px_int_n is high and TR control bit is set. When

cleared timer/counter is enabled whenever TR control bit

is set.

Timer or Counter selector. Cleared for timer operation

(input from system clock). Set for counter operation (input

from T input pin.

M1 M0

Operating

00

01

10

11

8048 Timer, TL serves as 5-bit prescaler.

16-bit Timer/Counter, TL and TH are cascaded.

8-bit auto-reload Timer/Counter, TH holds a value

which is to be loaded into TL.

timer 0: two 8-bit Timers/Counters. TL0 is controlled by

timer 0 control bits. TH0 is controlled by timer 1 control

bits. timer 1: stopped.

Fig.11 Timer/Counter Mode control (TMOD)

The Timer/Counter function is selected by control bits C/T

in the Timer Mode SFR (TMOD). These two

Timer/Counter have four operating modes, which are

selected by bit-pairs (M1.M0) in the TMOD. Refer to the

80C51 based 8-bit micro-controllers - Philips

Semiconductors (ref. IC20) for detail of the modes and

operation.

TL0/TL1 and TH0/TH1 are the actual timer/counter

registers for timer0 / timer1. TL0/TL1 is the low byte and

TH0/TH1 is the high byte.

TIMER WITH PRE-SCALER

An additional 16-bit timer with 8-bit pre-scaler is provided

to allow timer periods up to 16.777 seconds. This timer

remains active during IDLE mode.

TP2L sets the lower value of the period for timer 2 and

TP2H is the upper timer value. TP2PR provides an 8-bit

pre-scaler for timer 2. The value on TP2PR, TP2H and

TP2L shall never change unless updated by the software.

If the micro reads TP2R, TP2H orTP2L at any stage, this

should return the value written and not the current timer 2

value. The timer 2 should continue after overflow by

re-loading the timer with the values of SFRs TP2PR, TP2H

and TP2L.

TP2CL and TP2CH indicate the current timer 2 value.

These should be readable both when the timer 2 is active

and inactive. Once the timer 2 is disable, the timer 2 value

at the time of disabling should be maintained on the SFRs

TP2CL and TP2CH. At a count of zero (on TP2CL and

TP2CH), the overflow flag should be set:- TP2CRL<1> - ’0’

= no timer 2 overflow, ’1’= timer 2 overflow.

TP2CRL is the control and status for timer 2. TP2CRL.0 is

the timer enable and TP2CRL.1 is the timer overflow

status. The overflow flag will need to be reset by software.

Hence, if required, software may poll flag rather than use

interrupt. Upon overflow an interrupt should also be

generated.

Reset values of all registers should be 00 hex.

In Timer mode, Timer 2 should count down from the value

set on SFRs TP2PR, TP2H and TP2L. It is therefore

counting machine cycles. Since the machine cycle

consists of 12 oscillator periods, the count rate is 1/12 fosc

(1MHz).

Timer2 interval = (TP2H * 256 + TP2L) * (TP2PR + 1) * 1 us

WatchDog Timer

The WatchDog timer is a counter that once in an overflow

state forces the micro-controller in to a reset condition. The

purpose of the WatchDog timer is to reset the

micro-controller if it enters an erroneous processor state

(possibly caused by electrical noise or RFI) within a

reasonable period of time. When enabled, the WatchDog

circuitry will generate a system reset if the user program

fails to reload the WatchDog timer within a specified length

of time known as the WatchDog interval.

The WatchDog timer consists of an 8-bit counter with an

16-bit pre-scaler. The pre-scaler is fed with a signal whose

frequency is 1/12 fosc (1MHz).

The 8 bit timer is incremented every ‘t’ seconds where:

t=12x65536x1/fosc=12x65536x1/12x106 = 65.536ms

WATCHDOG TIMER OPERATION

The WatchDog operation is activated when the WLE bit in

the Power Control SFR (PCON) is set. The WatchDog can

be disabled by Software by loading the value 55H into the

WatchDog Key SFR (WDTKEY). This must be performed

before entering Idle/Power Down mode to prevent exiting

the mode prematurely.

Once activated the WatchDog timer SFR (WDT) must be

reloaded before the timer overflows. The WLE bit must be

set to enable loading of the WDT SFR, once loaded the

WLE bit is reset by hardware, this is to prevent erroneous

Software from loading the WDT SFR.

The value loaded into the WDT defines the WatchDog

interval.

WatchDog interval = (256 - WDT) * t = (256 -WDT) * 65.536ms.

The range of intervals is from WDT=00H which gives

16.777s to WDT=FFH which gives 65.536ms.

PORT Alternate Functions

The Ports 1,2 and 3 are shared with alternate functions to

enable control of external devices and circuitry. The

alternate functions are enabled by setting the appropriate

2001 Jan 18

33

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