TDA9351PS/N2 View Datasheet(PDF) - Philips Electronics

Part Name

Description

View to exact match

TDA9351PS/N2

TV signal processor-Teletext decoder with embedded micro-Controller

Philips Electronics 

Philips Semiconductors

TV signal processor-Teletext decoder with

embedded µ-Controller

Tentative Device Specification

TDA935X/6X/8X PS/N2 series

Names

ADD

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

M1,M0

Mode Control bits Timer/Counter 0.

M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler.

M1,M0 = 01, 16 bit time interval or event counter.

M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0.

M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter.

TP2CL

9CH TP2CL<7> TP2CL<6> TP2CL<5> TP2CL<4> TP2CL<3> TP2CL<2> TP2CL<1>

TP2CL<7:0> Indicate the low byte of the Time 2 current value.

TP2CH

9DH TP2CH<7> TP2CH<6> TP2CH<5> TP2CH<4> TP2CH<3> TP2CH<2> TP2CH<1>

TP2CH<7:0> Indicate the high byte of the Time 2 current value.

TP2H

92H TP2H<7>

TP2H<6>

TP2H<5>

TP2H<4>

TP2H<3>

TP2H<2>

TP2H<1>

TP2H<7:0> Timer 2 high byte, never change unless updated by the software.

TP2L

91H TP2L<7>

TP2L<6>

TP2L<5>

TP2L<4>

TP2L<3>

TP2L<2>

TP2L<1>

TP2L<7:0> Timer 2 low byte, never change unless updated by the software.

TP2PR

93H TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4> TP2PR<3> TP2PR<2> TP2PR<1>

TP2H<7:0> Timer 2 Pre-scaler, never change unless updated by the software.

TP2CRL

94H

-

-

-

-

-

-

TP2CRL<1>

TP2CRL<0>

Timer 2 Control.

0 - Timer 2 disabled.

1 - Timer 2 enabled.

TP2CRL<1>

Timer 2 Status.

0 - No Overflow.

1 - Overflow.

TEST

FDH TEST<7>

TEST<6>

TEST<5>

TEST<4>

TEST<3>

TEST<2>

TEST<1>

TEST<2:0>

Program Type bit SEL<2:0>.

011 - Display Dram test.

001 - Acquisition1 test.

010 - Acquisition2 test

TEST<4:3> Functional test mode bits, set via mode select logic.

TEST<7:5>

Dram Size.

000 - 1.5K x 16.

001 - 2K x 16.

010 - 6K x 16.

011 - 7K x 16.

100 - 12K x 16.

101 - 14K x 16.

110 - 1K x 16.

111 - 11K x 16.

TXT0

C0H X24 POSN

DISPLAY

X24

AUTO

FRAME

DISABLE

HEADER

ROLL

DISPLAY

STATUS

ROW

ONLY

DISABLE

FRAME

VPS ON

X24 POSN 0 - Store X/24 in extension memory

1 - Store X/24 in basic page memory with packets 0 to 23

Table 3 SFR Bit description

BIT0

RESET

TP2CL<0> 00H

TP2CH<0> 00H

TP2H<0>

00H

TP2L<0>

00H

TP2PR<0> 00H

TP2CRL<0>

00H

TEST<0>

00H

INV ON

00H

2001 Jan 18

21

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