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TDA9351PS/N2 View Datasheet(PDF) - Philips Electronics

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TDA9351PS/N2 Datasheet PDF : 118 Pages
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Philips Semiconductors
TV signal processor-Teletext decoder with
embedded µ-Controller
Tentative Device Specification
TDA935X/6X/8X PS/N2 series
FUNCTIONAL DESCRIPTION OF THE 80C51
The functionality of the micro-controller used on this
device is described here with reference to the industry
standard 80C51 micro-controller. A full description of its
functionality can be found in the 80C51 based 8-bit
micro-controllers - Philips Semiconductors (ref. IC20).
Features of the 80c51
80C51 micro-controller core standard instruction set and
timing.
1µs machine cycle.
Maximum 128K x 8-bit Program ROM.
Maximum of 12K x 8-bit Auxiliary RAM.
2K (OSD only version) Auxiliary RAM, maximum
of 1.25K required for Display
3K (1 page teletext version) Auxiliary RAM,
maximum of 2K required for Display
12K (10 page teletext version) Auxiliary RAM,
maximum of 10K required for Display
8-Level Interrupt Controller for individual enable/disable
with two level priority.
Two 16-bit Timer/Counters.
Additional 16-bit Timer with 8-bit Pre-scaler.
WatchDog Timer.
Auxiliary RAM Page Pointer.
16-bit Data pointer
Idle, Stand-by and Power-Down modes.
13 General I/O.
Four 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analogue signals.
One 14-bit PWM for Voltage Synthesis tuner control.
8-bit ADC with 4 multiplexed inputs.
2 high current outputs for directly driving LED’s etc.
I2C Byte Level bus interface.
Memory Organisation
The device has the capability of a maximum of 128K Bytes
of PROGRAM ROM and 12K Bytes of DATA RAM. The
OSD (& Closed Caption) only version has a 2K RAM and
a maximum of 64K ROM, the 1 page teletext version has
a 3K RAM and also a maximum of 64K ROM whilst the 10
page teletext version has a 12K RAM and a maximum of
128K ROM.
ROM Organisation
The 64K device has a continuous address space from 0 to
64K. The 128K is arranged in four banks of 32K. One of
the 32K banks is common and is always addressable. The
other three banks (Bank0, Bank1, Bank2) can be
accessed by selecting the right bank via the SFR ROMBK
bits 1/0.
FFFFH
Bank0
32K
8000H
FFFFH
Bank1
32K
8000H
FFFFH
Bank2
32K
8000H
7FFFH
Common
32K
0000H
Fig.4 ROM Bank Switching memory map
RAM Organisation
The Internal Data RAM is organised into two areas, Data
Memory and Special Function Registers (SFRs) as shown
in Fig.5.
FFH
Upper
128
80H
7FH
Lower
128
00H
Accessible
by Indirect
Addressing
only
Accessible
by Direct
Addressing
only
Accessible
by Direct
and Indirect
Addressing
Data Memory Special Function Registers
Fig.5 Internal Data Memory
DATA MEMORY
The Data memory is 256 x 8-bits and occupies the address
range 00 to FF Hex when using Indirect addressing and 00
to 7F Hex when using direct addressing. The SFRs occupy
the address range 80 Hex to FF Hex and are accessible
using Direct addressing only. The lower 128 Bytes of Data
memory are mapped as shown in Fig.6. The lowest 32
2001 Jan 18
11
 

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