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54LS194 View Datasheet(PDF) - Motorola => Freescale

Part NameDescriptionManufacturer
54LS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER Motorola
Motorola => Freescale Motorola
54LS194 Datasheet PDF : 4 Pages
1 2 3 4
SN54 / 74LS194A
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
ts
th
trec
Parameter
Clock or MR Pulse Width
Mode Control Setup Time
Data Setup Time
Hold time, Any Input
Recovery Time
Limits
Min Typ Max Unit
20
ns
30
ns
20
ns
0
ns
25
ns
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME(ts) —is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
CLOCK
tPHL
OUTPUT
1/fmax
1.3 V
tW
1.3 V
1.3 V
tPLH
1.3 V
OTHER CONDITIONS: S1 = L, MR = H, S0 = H
Figure 1. Clock to Output Delays Clock Pulse
Width and fmax
S0
S1
DSR DSL
P0 P1 P2 P3
th(L) = 0
CLOCK
OUTPUT*
ts(L)
1.3 V
(––– IS SHIFT LEFT)
ts(L)
th(L) = 0
ts(H)
th(H) = 0
1.3 V
1.3 V
ts(H)
th(H) = 0
MR
CLOCK
OUTPUT
1.3 V
tW
trec
1.3 V
tPHL
1.3 V
OTHER CONDITIONS: S0, S1 = H
OTHER CONDITIONS: PO = P1 = P2 = P3 = H
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
OTHER CONDITIONS: MR = H
OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY
OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(DSR, DSL) and Parallel Data (P0, P1, P2, P3)
(STABLE TIME)
S0 S1
CLOCK
ts
th = 0
th = 0
1.3 V
1.3 V
ts
1.3 V
OTHER CONDITIONS: MR = H
Figure 4. Setup (ts) and Hold (th) Time for S Input
FAST AND LS TTL DATA
5-4
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