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54LS194 View Datasheet(PDF) - Motorola => Freescale

Part NameDescriptionManufacturer
54LS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER Motorola
Motorola => Freescale Motorola
54LS194 Datasheet PDF : 4 Pages
1 2 3 4
LOGIC DIAGRAM
P0
10
3
S1
9
S0
2
DSR
SN54 / 74LS194A
P1
P2
4
5
P3
6
7
DSL
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
11
CP
1
MR
S Q0
CP
R
CLEAR
15
Q0
S Q1
CP
R
CLEAR
14
Q1
S Q2
CP
R
CLEAR
13
Q2
S Q3
CP
R
CLEAR
12
Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
characteristics of the LS194A 4-Bit Bidirectional Shift Regis-
ter. The LS194A is similar in operation to the Motorola LS195A
Universal Shift Register when used in serial or parallel data
register transfers. Some of the common features of the two
devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations taking
place in less than 15 ns (typical) making the device especially
useful for implementing very high speed CPUs, or the memory
buffer registers.
The four parallel data inputs (P0, P1, P2, P3) are D-type
inputs. When both S0 and S1 are HIGH, the data appearing on
P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and
Q3 outputs respectively following the next LOW to HIGH
transition of the clock.
The asynchronous Master Reset (MR), when LOW, over-
rides all other input conditions and forces the Q outputs LOW.
Special logic features of the LS194A design which increase
the range of application are described below:
Two mode control inputs (S0, S1) determine the synchro-
nous operation of the device. As shown in the Mode Selection
Table, data can be entered and shifted from left to right (shift
right, Q0 Q1, etc.) or right to left (shift left, Q3 Q2, etc.), or
parallel data can be entered loading all four bits of the register
simultaneously. When both S0 and S1,are LOW, the existing
data is retained in a “do nothing” mode without restricting the
HIGH to LOW clock transition.
D-type serial data inputs (DSR, DSL) are provided on both
the first and last stages to allow multistage shift right or shift left
data transfers without interfering with parallel load operation.
MODE SELECT — TRUTH TABLE
OPERATING MODE
Reset
INPUTS
OUTPUTS
MR
S1
S0
DSR
DSL
Pn
Q0 Q1
Q2
Q3
L
X
X
X
X
X
L
L
L
L
Hold
H
I
I
X
X
X
q0
q1
q2
q3
Shift Left
H
h
I
X
I
X
q1
q2
q3
L
H
h
I
X
h
X
q1
q2
q3
H
Shift Right
H
I
h
I
X
X
L
q0
q1
q2
H
I
h
h
X
X
H
q0
q1
q2
Parallel Load
H
h
h
X
X
Pn
P0 P1
P2
P3
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
FAST AND LS TTL DATA
5-2
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