ADP7118ARDZ-2.5 View Datasheet(PDF) - Analog Devices

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Description

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ADP7118ARDZ-2.5

20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator

Analog Devices 

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

VIN to GND

VOUT to GND

EN to GND

SENSE/ADJ to GND

SS to GND

Storage Temperature Range

Junction Temperature (TJ)

Operating Ambient Temperature (TA)

Range

Soldering Conditions

Rating

–0.3 V to +24 V

–0.3 V to VIN

–0.3 V to +24 V

–0.3 V to +6 V

–0.3 V to VIN or +6 V

(whichever is less)

–65°C to +150°C

150°C

–40°C to +125°C

JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in

combination. The ADP7118 can be damaged when the junction

temperature limits are exceeded. Monitoring ambient temperature

does not guarantee that TJ is within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

In applications with moderate power dissipation and low

printed circuit board (PCB) thermal resistance, the maximum

ambient temperature can exceed the maximum limit as long as

the junction temperature is within specification limits. The

junction temperature of the device is dependent on the ambient

temperature, the power dissipation (PD) of the device, and the

junction-to-ambient thermal resistance of the package (θJA).

Maximum TJ is calculated from the TA and PD using the formula

TJ = TA + (PD × θJA)

(1)

ADP7118

θJA of the package is based on modeling and calculation using a

4-layer board. The θJA is highly dependent on the application

and board layout. In applications where high maximum power

dissipation exists, close attention to thermal board design is

required. The value of θJA may vary, depending on PCB material,

layout, and environmental conditions. The specified values of

θJA are based on a 4-layer, 4 inches × 3 inches circuit board. See

JESD51-7 and JESD51-9 for detailed information on the board

construction.

ΨJB is the junction-to-board thermal characterization parameter

with units of °C/W. The ΨJB of the package is based on modeling

and calculation using a 4-layer board. The JESD51-12, Guidelines

for Reporting and Using Electronic Package Thermal Information,

states that thermal characterization parameters are not the same

as thermal resistances. ΨJB measures the component power flowing

through multiple thermal paths rather than a single path as in

thermal resistance (θJB). Therefore, ΨJB thermal paths include

convection from the top of the package as well as radiation from

the package, factors that make ΨJB more useful in real-world

applications. Maximum TJ is calculated from the board

temperature (TB) and PD using the formula

TJ = TB + (PD × ΨJB)

(2)

See JESD51-8 and JESD51-12 for more detailed information

about ΨJB.

THERMAL RESISTANCE

θJA, θJC, and ΨJB are specified for the worst-case conditions, that

is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type

θJA

θJC

ΨJB

Unit

6-Lead LFCSP

72.1 42.3 47.1 °C/W

8-Lead SOIC

52.7 41.5 32.7 °C/W

5-Lead TSOT

170

N/A1 43

°C/W

1 N/A means not applicable.

ESD CAUTION

Rev. C | Page 5 of 23

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