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ADP7118ARDZ-3.3 View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADP7118ARDZ-3.3 Datasheet PDF : 23 Pages
First Prev 21 22 23
ADP7118
OUTLINE DIMENSIONS
Data Sheet
PIN 1 INDEX
AREA
0.60
0.55
0.50
SEATING
PLANE
2.10
2.00 SQ
1.90
1.70
1.60
1.50
4
0.65 BSC
6
0.15 REF
TOP VIEW
0.425
0.350
0.275
EXPOSED
PAD
1.10
1.00
0.90
3
BOTTOM VIEW
0.20 MIN
1
PIN 1
INDICATOR
(R 0.15)
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.35
SECTION OF THIS DATA SHEET.
0.30
0.20 REF
0.25
Figure 67. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD]
2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead
(CP-6-3)
Dimensions shown in millimeters
5.00
4.90
2.29
4.80
0.356
8
5
6.20
4.00 6.00
3.90 5.80
3.80
0.457
1
4
1.27 BSC
1.75
1.35
TOP VIEW
3.81 REF
1.65
1.25
BOTTOM VIEW
0.50 45°
0.25
SEATING
PLANE
0.10 MAX
0.51
0.31
0.05 NOM
COPLANARITY 0°
0.10
1.04 REF
2.29
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.25
0.17
1.27
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-A A
Figure 68. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
Rev. C | Page 22 of 23
 

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