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ADP7118UJ-EVALZ View Datasheet(PDF) - Analog Devices

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ADP7118UJ-EVALZ Datasheet PDF : 23 Pages
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Data Sheet
THEORY OF OPERATION
The ADP7118 is a low quiescent current, LDO linear regulator
that operates from 2.7 V to 20 V and provides up to 200 mA of
output current. Drawing a low 180 μA of quiescent current
(typical) at full load makes the ADP7118 ideal for portable
equipment. Typical shutdown current consumption is less than
3 µA at room temperature.
Optimized for use with small 2.2 µF ceramic capacitors, the
ADP7118 provides excellent transient performance.
VIN
GND
SHORT-CIRCUIT,
THERMAL
PROTECTION
REFERENCE
VOUT
SENSE/
ADJ
EN
SHUTDOWN
Figure 42. Internal Block Diagram
Internally, the ADP7118 consists of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass
transistor. Output current is delivered via the PMOS pass
device, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the
feedback voltage is lower than the reference voltage, the gate of
the PMOS device is pulled lower, allowing more current to pass
and increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the gate of the PMOS device
is pulled higher, allowing less current to pass and decreasing the
output voltage.
ADP7118
The ADP7118 is available in 16 fixed output voltage options,
ranging from 1.2 V to 5.0 V. The ADP7118 architecture allows
any fixed output voltage to be set to a higher voltage with an
external voltage divider. For example, a fixed 5 V output can be
set to a 6 V output according to the following equation:
VOUT = 5 V(1 + R1/R2)
(3)
where R1 and R2 are the resistors in the output voltage divider
shown in Figure 43.
To set the output voltage of the adjustable ADP7118, replace
5 V in Equation 3 with 1.2 V.
VIN = 7V
CIN
2.2µF
ADP7118
VIN
VOUT
SENSE/ADJ
ON
OFF
EN GND SS
VOUT = 6V
R1
COUT
2kΩ
2.2µF
R2
10kΩ
CSS
1nF
Figure 43. Typical Adjustable Output Voltage Application Schematic
It is recommended that the R2 value be less than 200 kΩ to
minimize errors in the output voltage caused by the SENSE/ADJ
pin input current. For example, when R1 and R2 each equal 200 kΩ
and the default output voltage is 1.2 V, the adjusted output voltage is
2.4 V. The output voltage error introduced by the SENSE/ADJ pin
input current is 1 mV or 0.04%, assuming a typical SENSE/ADJ pin
input current of 10 nA at 25°C.
The ADP7118 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is
high, VOUT turns on, and when EN is low, VOUT turns off.
For automatic startup, EN can be tied to VIN.
Rev. C | Page 13 of 23
 

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