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PIC32MX120F064H View Datasheet(PDF) - Microchip Technology

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
TABLE 3-3:
Exception
Reset
DSS
DINT
NMI
Interrupt
DIB
AdEL
IBE
DBp
Sys
Bp
RI
CpU
CEU
Ov
Tr
DDBL/DDBS
AdEL
AdES
DBE
DDBL
MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES
Description
Assertion MCLR or a Power-on Reset (POR).
EJTAG debug single step.
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
Assertion of NMI signal.
Assertion of unmasked hardware or software interrupt signal.
EJTAG debug hardware instruction break matched.
Fetch address alignment error. Fetch reference to protected address.
Instruction fetch bus error.
EJTAG breakpoint (execution of SDBBP instruction).
Execution of SYSCALL instruction.
Execution of BREAK instruction.
Execution of a reserved instruction.
Execution of a coprocessor instruction for a coprocessor that is not enabled.
Execution of a CorExtend instruction when CorExtend is not enabled.
Execution of an arithmetic instruction that overflowed.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
Load address alignment error. Load reference to protected address.
Store address alignment error. Store to protected address.
Load or store bus error.
EJTAG data hardware breakpoint matched in load data compare.
3.3 Power Management
The MIPS® M4K® processor core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or Halting the clocks, which reduces
system power consumption during Idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 27.0
“Power-Saving Features”.
3.3.2 LOCAL CLOCK GATING
The majority of the power consumed by the PIC32MX-
1XX/2XX/5XX 64/100-pin family core is in the clock
tree and clocking registers. The PIC32MX family uses
extensive use of local gated-clocks to reduce this
dynamic power consumption.
3.4 EJTAG Debug Support
The MIPS® M4K® processor core provides for an
Enhanced JTAG (EJTAG) interface for use in the soft-
ware debug of application and kernel code. In addition
to standard User mode and Kernel modes of operation,
the M4K® core provides a Debug mode that is entered
after a debug exception (derived from a hardware
breakpoint, single-step exception, etc.) is taken and
continues until a Debug Exception Return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans-
ferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.
DS60001290E-page 38
2014-2017 Microchip Technology Inc.
 

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