JS28F128J3D-75 View Datasheet(PDF) - Numonyx -> Micron

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Description

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JS28F128J3D-75

Numonyx™ Embedded Flash Memory (J3 v D)

Numonyx -> Micron 

Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)

C

Table 12: Write Operations

#

Symbol

Parameter

Density

Valid for All

Speeds

Min

Max

Unit

Notes

32 Mbit

150

1,2,3

64 Mbit

180

W1

tPHWL (tPHEL) RP# High Recovery to WE# (CEX) Going Low

128 Mbit 210

256 Mbit 210

W2

tELWL (tWLEL) CEX (WE#) Low to WE# (CEX) Going Low

0

1,2,4

W3

tWP

Write Pulse Width

60

1,2,4

W4 tDVWH (tDVEH) Data Setup to WE# (CEX) Going High

50

1,2,5

W5 tAVWH (tAVEH) Address Setup to WE# (CEX) Going High

W6 tWHEH (tEHWH) CEX (WE#) Hold from WE# (CEX) High

55

1,2,5

ns

0

1,2,

W7 tWHDX (tEHDX) Data Hold from WE# (CEX) High

W8 tWHAX (tEHAX) Address Hold from WE# (CEX) High

0

All

0

1,2,

1,2,

W9

tWPH

Write Pulse Width High

30

1,2,6

W11 tVPWH (tVPEH) VPEN Setup to WE# (CEX) Going High

0

1,2,3

W12 tWHGL (tEHGL) Write Recovery before Read

35

1,2,7

W13 tWHRL (tEHRL) WE# (CEX) High to STS Going Low

500

1,2,8

W15

tQVVL

VPEN Hold from Valid SRD, STS Going High

0

1,2,3,8,9

Notes:

CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that

disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on page 31).

1.

Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during

read-only operations. Refer to AC Characteristics–Read-Only Operations.

2.

A write operation can be initiated and terminated with either CEX or WE#.

3.

Sampled, not 100% tested.

4.

Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high

(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.

5.

Refer to Table 17, “Enhanced Configuration Register” on page 33 for valid AIN and DIN for block erase,

program, or lock-bit configuration.

6.

Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going

low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.

7.

For array access, tAVQV is required in addition to tWHGL for any accesses after a write.

8.

STS timings are based on STS configured in its RY/BY# default mode.

9.

VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[5:3,1] =

0).

December 2007

316577-06

Datasheet

27

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