GMS81604/08
LG Semicon
8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP2 of timer mode register
TM2 for Timer 2) as shown in Figure 21. In this mode,
Timer 1 still operates as an 8-bit timer/counter.
As mentioned above, not only Timer 0 but Timer 2 can
also be used as a capture mode.
In 8-bit capture mode, Timer 1 and Timer 3 are can not
be used as a capture mode.
The Timer/Counter register is incremented in response
internal or external input. This counting function is
same with normal timer mode, but Timer interrupt is
not generated. Timer/Counter still does the above, but
with the added feature that a edge transition at external
input INTx pin causes the current value in the Timer x
register (T0,T2), to be captured into registers CDRx
(CDR0, CDR2), respectively. After captured, Timer
x register is cleared and restarts by hardware.
Caution:
The CDRx and TDRx are in same address.
In the capture mode, reading operation is read the
CDRx, not TDRx because path is opened to the
CDRx.
It has three transition modes: "falling edge", "rising
edge", "both edge" which are selected by interrupt
edge selection register IEDS (Refer to External inter-
rupt section). In addition, the transition at INTx pin
generate an interrupt.
EC0 PIN
XIN PIN
MSB
TM0
CAP0
1
T1ST T1SL1 T1SL0 T0ST
X
≠0
≠0
X
LSB
T0CN
X
T0SL1
T
0
ADDRE
SRLE0S E T
SS: E2H
VALUE:
00H
X
X
T0SL[1:0]
EDGE DETECTOR
÷4
÷ 16
÷ 64
PRESCALER
MUX
IEDS[1:0]
0
1
T0CN
T0ST
0: Stop
1: Clear and Start
T0 (8-BITS)
CAPTURE
THIS FIGURE IS A EXAMPLE OF THE TIMER 0.
IN THE TIMER 2, EACH REGISTERS AND FLAGS
MAY BE CHANGED CORRESPONDINGLY.
CDR0 (8-BITS)
INT0 PIN
INT0IF
INT0
INTERRUPT
Figure 21. 8-bit Capture Mode
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