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GMS81604 View Datasheet(PDF) - Hyundai Micro Electronics

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GMS81604 Datasheet PDF : 79 Pages
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LG Semicon
GMS81604/08
TIMER/COUNTER
The GMS81604 has four Timer/Counter registers.
Each module can generate an interrupt to indicate that
an event has occurred (i.e. timer match).
Timer 0 and Timer 1 are can be used either the two
8-bit Timer/Counter or one 16-bit Timer/Counter to
combine them. Also Timer 2 and Timer 3 are same.
In the "timer" function, the register is incremented
every internal clock input. Thus, one can think of it as
counting internal clock input. Since a least clock con-
sists of 4 and most clock consists of 64 oscillator
periods, the count rate is 1/4 to 1/64 of the oscillator
frequency.
In the "counter" function, the register is incremented
in response to a 1-to-0 (falling edge) transition at its
corresponding external input pin, EC0 or EC2.
In addition the "capture" function, the register is incre-
mented in response external or internal clock sources
same with timer or counter function. When external
clock edge input, the count register is captured into
Timer data register correspondingly.
It has four operating modes: "8-bit timer/counter",
"16-bit timer/counter", "8-bit capture", "16-bit cap-
ture" which are selected by bit in Timer mode register
TM0 and TM2 as shown in right Table.
In operation of Timer 2, Timer 3, their operations are
same with Timer 0, Timer 1, respectively.
TM0 FOR TIMER 0, TIMER 1
CAP0 T1SL1 T 1 S L 0
Timer 0
Timer 1
0
0
0
16-bit Timer/Counter
1
0
0
16-bit Capture
0
X
X 8-bit Timer
8-bit Timer
1
X
X 8-bit Capture 8-bit Timer
TM2 FOR TIMER 2, TIMER 3
CAP2 T 3 S L 1 T 3 S L 0
Timer 2
Timer 3
0
0
0
16-bit Timer/Counter
1
0
0
16-bit Capture
0
X
X 8-bit Timer
8-bit Timer
1
X
X 8-bit Capture 8-bit Timer
TM0
TM2 is in Figure 14.
MSB
LSB
CAP0 T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0
TIMER 1
TIMER 0
ADDRESS: E2H
RESET VALUE: 00H
CAP0 Capture mode selection flag, When set, timer
operate as one 16-bit capture timer combine
two 8-bit timers.
T0ST
When set, The Timer 0 Count Register is
cleared and start again.
When cleared, stop the counting.
T1ST
When set, Timer 1 count register is cleared
and start again.
When cleared, stop the counting.
TIMER 1
T1SL1 T1SL0 INPUT CLOCK
0
0 16-BIT TIMER MODE (NOTE 1)
0
1 8-BIT TIMER, ÷ 4 PRESCALER
1
0 8-BIT TIMER, ÷ 16
1
1 8-BIT TIMER, ÷ 64
T0CN Start/Stop control for Timer 0. A logic 1
starts the timer.
TIMER 0
T0SL1 T0SL0 INPUT CLOCK
0
0 Timer or Counter select
0
1 ÷ 4 PRESCALER
1
0 ÷ 16
1
1 ÷ 64
NOTE:
If this mode selected, the Timer 0 are used as a 16-bit timer mode. The Timer 1 is engaged to the Timer 0.
The source clock is selected by bits T0SL1 and T0SL0.
Figure 13. TM0: Timer 0, Timer 1 Mode Register
27
 

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