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GMS81604 View Datasheet(PDF) - Hyundai Micro Electronics

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GMS81604 Datasheet PDF : 79 Pages
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GMS81604/08
LG Semicon
BASIC INTERVAL TIMER
The GMS81604 has one 8-bit Basic Interval Timer that
is free-run, can not stop. Block diagram is shown in
Figure 11.
The 8-bit Basic interval timer register (BITR) is incre-
mented every internal count pulse which is divided by
prescaler. Since prescaler has divided ratio by 16 to
2048, the count rate is 1/16 to 1/2048 of the oscillator
frequency. As the count overflows from FFH to 00H,
this overflow causes to generate the Basic interval
timer interrupt. The BITR is interrupt request flag of
Basic interval timer.
Caution:
All control bits of Basic interval timer are in
CKCTLR register which is located at same ad-
dress of BITR (address D3H). Address D3H is
read as BITR, written to CKCTLR.
When write "1" to bit BTCL of CKCTLR, data register
is cleared to "0" and restart to count-up. It becomes "0"
after one machine cycle by hardware.
XIN PIN
BTS[2:0]
÷16
÷32
÷64
÷128
8
÷256
÷512
÷1024
÷2048
3
MUX
PRESCALER
BTCL
CLEAR
BITR (8 BITS)
BITIF
BASIC INTERVAL TIMER
INTERRUPT
Figure 11. Block Diagram of The Basic Interval Timer
CKCTLR
-
- WDTON ENPCK BTCL BTS2 BTS1 BTS0
ADDRESS: D3H
RESET VALUE: --010111
Symbol
WDTON
ENPCK
BTCL
Position
CKCTLR.5
CKCTLR.4
CKCTLR.3
Name and Significance
WDTON=1, enables Watch Dog Timer operation,
WDTON=0, operates as a 6-bit timer
Enable Peripheral clock.
BTCL is set to "1", BITR is cleared. BTCL becomes "0" automatically
after one machine cycle, and starts counting.
BASIC INTERVAL TIMER CLOCK SELECTION
BTS2
BTS1
BTS0
Prescale value
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
16
32
64
128
256
512
1024
2048
Figure 12. CKCTLR: Control Clock Register
26
 

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