GMS81604 View Datasheet(PDF) - Hyundai Micro Electronics

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GMS81604

LG Semicon. CMOS single-chip 8-bit microcontroller. ROM size 8K bytes. 256 bytes of on-chip data RAM

Hyundai Micro Electronics 

LG Semicon

GMS81604/08

PSW

MSB

LSB

NVGBH I Z C

RESET VALUE: 00H

NEGATIVE FLAG

CARRY FLAG RECEIVES

CARRY OUT

OVERFLOW FLAG

ZERO FLAG

G FLAG TO SELECT DIRECT PAGE

BRK FLAG

INTERRUPT ENABLE

FLAG

HALF CARRY FLAG RECEIVES

CARRY OUT FROM BIT 1 OF

ADDITION OPERANDS

Figure 6. PSW (Program Status Word) Register

BRK instruction. All interrupts are disabled when

cleared to "0". This flag immediately becomes "0"

when an interrupt is served. It is set by the EI instruc-

tion, cleared by the DI instruction.

[Half carry flag H]

After operation, set when there is a carry from bit 3 of

ALU or there is not a borrow from bit 4 of ALU. This

bit can not be set or cleared except CLRV instruction,

clearing with Overflow flag (V).

[Break flag B]

This flag set by software BRK instruction to distin-

guish BRK from TCALL instruction which as the

same vector address.

[Direct page flag G]

This flag assign direct page for direct addressing mode.

In the direct addressing mode, addressing area is

within zero page 00H to FFH when this flag is "0". If it

is set to "1", addressing area is 100H to 1FFH.

It is set by SETG instruction, and cleared by CLRG.

[Overflow flag V]

This flag is set to "1" when an overflow occurs in the

result of an arithmetic operation involving signs. An

overflow occurs when the result of an addition or

subtraction exceeds +127(7FH) or -128(80H).

The CLRV instruction clears the overflow flag. There

is no set instruction. When the BIT instruction is

executed, for other than the above, bit 6 of memory is

copy to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the

result of a data or arithmetic operation. When the BIT

instruction is executed, bit 7 of memory is copy to this

flag.

1) INTERRUPT

M(SP) ← (PCH)

SP ← SP - 1

M(SP) ← (PCL)

SP ← SP - 1

M(SP) ← (PSW)

SP ← SP - 1

2) RETI

SP ← SP + 1

(PSW) ← M(SP)

SP ← SP + 1

(PCL) ← M(SP)

SP ← SP + 1

(PCH) ← M(SP)

3) CALL

M(SP) ← (PCH)

SP ← SP - 1

M(SP) ← (PCL)

SP ← SP - 1

4) RET

SP ← SP + 1

(PCL) ← M(SP)

SP ← SP + 1

(PCH) ← M(SP)

5) PUSH A (X,Y,PSW)

M(SP) ← ACC.

SP ← SP - 1

6) POP A (X,Y,PSW)

SP ← SP + 1

M(SP) ← (PCH)

Figure 7. Stack Operation

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