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R5F21143DSP View Datasheet(PDF) - Renesas Electronics

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R5F21143DSP Datasheet PDF : 277 Pages
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R8C/14 Group, R8C/15 Group
8. Bus
8. Bus
During access, the ROM/RAM and SFR vary from bus cycles. Table 8.1 lists Bus Cycles for Access Space
of the R8C/14 Group and Table 8.2 lists Bus Cycles for Access Space of the R8C/15 Group.
The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word-(16 bits)
unit, these area are accessed twice in 8-bit unit. Table 8.3 lists Access Unit and Bus Operation.
Table 8.1 Bus Cycles for Access Space of the R8C/14 Group
Access Area
SFR
ROM/RAM
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
Table 8.2 Bus Cycles for Access Space of the R8C/15 Group
Access Area
SFR/Data flash
Program ROM/RAM
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
Table 8.3 Access Unit and Bus Operation
Area
Even Address
Byte Access
CPU Clock
Address
Data
Odd Address
Byte Access
CPU Clock
Address
Data
Even Address
Word Access
CPU Clock
Address
Data
SFR, Data flash
Even
Data
Odd
Data
Even
Data
Even+1
Data
Odd Address
Word Access
CPU Clock
Address
Data
Odd
Data
Odd+1
Data
ROM (Program ROM), RAM
CPU Clock
Address
Data
Even
Data
CPU Clock
Address
Data
CPU Clock
Address
Data
Odd
Data
Even
Data
Even+1
Data
CPU Clock
Address
Data
Odd
Data
Odd+1
Data
Rev.2.10 Jan 19, 2006 Page 37 of 253
REJ09B0164-0210
 

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