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R5F21142SP-U0 View Datasheet(PDF) - Renesas Electronics

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R5F21142SP-U0 Datasheet PDF : 277 Pages
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R8C/14 Group, R8C/15 Group
6. Voltage Detection Circuit
Voltage Monitor 2 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VW2C
Bit Symbol
Address
0037h
Bit Name
After Reset(8)
00h
Function
RW
Voltage Monitor 2 Interrupt / 0 : Disable
VW2C0 Reset Enable Bit(6, 10)
1 : Enable
RW
Voltage Monitor 2 Digital Filter 0 : Digital filter enabled mode
Disable Mode Select Bit(2)
(digital filter circuit enabled)
VW2C1
1 : Digital filter disabled mode
RW
(digital filter circuit disabled)
Voltage Change Detection
0 : Not detected
VW2C2 Flag(3,4,8)
1 : Vdet2 pass detected
RW
WDT Detection Flag(4,8)
0 : Not detected
VW2C3
1 : Detected
RW
Sampling Clock Select Bit
b5 b4
VW2F0
0 0 : fRING-S divide-by-1
RW
0 1 : fRING-S divide-by-2
VW2F1
1 0 : fRING-S divide-by-4
1 1 : fRING-S divide-by-8
RW
Voltage Monitor 2 Circuit Mode 0 : Voltage monitor 2 interrupt mode
VW2C6 Select Bit(5)
1 : Voltage monitor 2 reset mode
RW
Voltage Monitor 2 Interrupt / 0 : When VCC reaches Vdet2 or above
VW2C7 Reset Generation Condition
1 : When VCC reaches Vdet2 or below
RW
Select Bit(7,9)
NOTES :
1. Set the PRC3 bit in the PRCR register to “1” (rew rite enable) before w riting to this register.
When rew riting the VW2C register, the VW2C2 bit may be set to “1”. Set the VW2C2 bit to “0” after rew riting the
VW2C register.
2. When the voltage monitor 2 interrupt is used to exit stop mode and to return again, w rite “0” to the VW2C1
bit before w riting “1”.
3. This bit is enabled w hen the VCA27 bit in the VCA2 register is set to “1” (voltage detection 2 circuit
enabled).
4. Set this bit to “0” by a program. When w riting “0” by a program, it is set to “0” (It remains unchanged even if it is set
to “1”).
5. This bit is enabled w hen the VW2C0 bit is set to “1” (voltage monitor 2 interrupt / enables reset).
6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to “1” (voltage detection 2 circuit
enabled). Set the VW2C0 bit to “0” (disable) w hen the VCA27 bit is set to “0” (voltage detection 2 circuit disabled).
7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to “1” (digital filter disabled mode).
8. The VW2C2 and VW2C3 bits remain unchanged in the softw are reset, w atchdog timer reset and voltage monitor 2
reset.
9. When the VW2C6 bit is set to “1” (voltage monitor 2 reset mode), set the VW2C7 bit to “1” (w hen VCC
reaches to Vdet2 or below )(do not set to “0”).
10. Set the VW2C0 bit to “0” (disabled) under the conditions of the VCA13 bit in the VCA1 register set to “1” (VCC
Vdet2 or voltage detection 2 circuit disabled), the VW2C1 bit set to “1” (digital filter disabled mode) and the VW2C7
bit set to “0” (w hen VCC reaches Vdet2 or above).
Set the VW2C0 bit to “0” (disabled) under the conditions of the VCA13 bit set to “0” (VCC < Vdet2), the VW2C1 bit
set to “1” (digital filter disabled mode) and the VW2C7 bit set to “1” (w hen VCC reaches Vdet2 or below ).
Figure 6.6 VW2C Register
Rev.2.10 Jan 19, 2006 Page 30 of 253
REJ09B0164-0210
 

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