XMEM Register
Description
MCU Control Register –
MCUCR
Extended MCU Control
Register – EMCUCR
ATmega8515(L)
Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)
T1
T2
T3
T4
T5
System Clock (CLKCPU)
T6
T7
ALE
A15:8 Prev. Addr.
Address
DA7:0 Prev. Data
Address XX
Data
WR
DA7:0 (XMBK = 0) Prev. Data
Address
Data
DA7:0 (XMBK = 1) Prev. Data
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector)
The ALE pulse in period T7 is only present if the next instruction accesses the RAM
(internal or external).
Bit
Read/Write
Initial Value
7
6
5
SRE SRW10
SE
R/W
R/W
R/W
0
0
0
4
SM1
R/W
0
3
ISC11
R/W
0
2
ISC10
R/W
0
1
ISC01
R/W
0
0
ISC00
R/W
0
MCUCR
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit over-
rides any pin direction settings in the respective Data Direction Registers. Writing SRE
to zero, disables the External Memory Interface and the normal pin and data direction
settings are used.
• Bit 6 – SRW10: Wait State Select Bit
For a detailed description, see common description for the SRWn bits below (EMCUCR
description).
Bit
Read/Write
Initial Value
7
SM0
R/W
0
6
SRL2
R/W
0
5
SRL1
R/W
0
4
SRL0
R/W
0
3
SRW01
R/W
0
2
SRW00
R/W
0
1
SRW11
R/W
0
0
ISC2
R/W
0
EMCUCR
• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit
It is possible to configure different wait states for different external memory addresses.
The External Memory address space can be divided in two sectors that have separate
wait state bits. The SRL2, SRL1, and SRL0 bits select the splitting of these sectors, see
Table 2 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and
the entire External Memory address space is treated as one sector. When the entire
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