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MT3333 View Datasheet(PDF) - MediaTek Inc

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MT3333 All-in-One GNSS
Datasheet
SCK
SCS#
SO
SIN
T1
MSB
T3
T4
MSB
T2
LSB
T3
T4
LSB
T5
T6
T5
T6
Figure 7-2: Timing diagram of the SPI interface
7.3. I2C interface timing
Symbol
T1
T2
T3
T4
Period
(MM_CNT_PHASE_VAL0+1)/TCXO_CLK
(MM_CNT_PHASE_VAL1+1)/TCXO_CLK
(MM_CNT_PHASE_VAL2+1)/TCXO_CLK
(MM_CNT_PHASE_VAL3+1)/TCXO_CLK
Note: The condition of I2C clock cycle (I2C_CLK) is (TCXO_CLK/4) MHz ~ (TCXO_CLK/(MM_CNT+4)) MHz. The
MM_CNT is the sum of MM_CNT_PHASE_VAL0, MM_CNT_PHASE_VAL1, MM_CNT_PHASE_VAL2 and
MM_CNT_PHASE_VAL3 in full speed mode.
I2C_SDA
I2C_SCL
T1
T2
T3
T4
Figure 7-3: Timing diagram of the I2C interface
© 2016 - 2017 MediaTek Inc.
Page 20 of 22
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
 

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