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ADC0805 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADC0805 8-Bit P Compatible A/D Converters TI
Texas Instruments TI
ADC0805 Datasheet PDF : 48 Pages
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ADC0801, ADC0802
ADC0803, ADC0804, ADC0805
SNOSBI1B – NOVEMBER 2009 – REVISED FEBRUARY 2013
AC ELECTRICAL CHARACTERISTICS
The following specifications apply for VCC=5 VDC and TMINTATMAX (unless otherwise specified)
PARAMETER
CONDITIONS
MIN TYP
TC
Conversion Time
fCLK = 640 kHz(1)
103
See (2) (1)
66
Clock Frequency
fCLK
Clock Duty Cycle
VCC = 5V(2)
100 640
40%
CR
tW(WR)L
tACC
Conversion Rate in Free-Running Mode
Width of WR Input (Start Pulse Width)
Access Time (Delay from Falling Edge of RD
to Output Data Valid)
INTR tied to WR with CS = 0 VDC,
fCLK = 640 kHz
CS = 0 VDC (3)
CL = 100 pF
8770
100
135
t1H, t0H
TRI-STATE Control (Delay from Rising Edge of CL = 10 pF, RL = 10k (See TRI-STATE
RD to Hi-Z State)
TEST CIRCUITS AND WAVEFORMS)
125
tWI, tRI
Delay from Falling Edge of WR or RD to Reset
of INTR
300
CIN
Input Capacitance of Logic Control Inputs
5
COUT
TRI-STATE Output Capacitance (Data Buffers)
5
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1) Logical “1” Input Voltage (Except Pin 4 CLK IN) VCC = 5.25 VDC
VIN (0) Logical “0” Input Voltage (Except Pin 4 CLK IN) VCC = 4.75 VDC
IIN (1)
Logical “1” Input Current (All Inputs)
VIN = 5 VDC
IIN (0)
Logical “0” Input Current (All Inputs)
VIN = 0 VDC
CLOCK IN AND CLOCK R
2
0.005
–1 –0.005
VT+
CLK IN (Pin 4) Positive Going Threshold
Voltage
2.7 3.1
VT
CLK IN (Pin 4) Negative Going Threshold
Voltage
1.5 1.8
VH
CLK IN (Pin 4) Hysteresis (VT+)–(VT)
VOUT (0) Logical “0” CLK R Output Voltage
VOUT (1) Logical “1” CLK R Output Voltage
DATA OUTPUTS AND INTR
IO = 360 µA, VCC = 4.75 VDC
IO = 360 µA, VCC = 4.75 VDC
0.6 1.3
2.4
Logical “0” Output Voltage
VOUT (0) Data Outputs
INTR Output
VOUT (1) Logical “1” Output Voltage
IOUT
TRI-STATE Disabled Output Leakage (All Data
Buffers)
ISOURCE
ISINK
POWER SUPPLY
IOUT = 1.6 mA, VCC = 4.75 VDC
IOUT = 1.0 mA, VCC = 4.75 VDC
IO = 360 µA, VCC = 4.75 VDC
IO = 10 µA, VCC = 4.75 VDC
VOUT = 0 VDC
VOUT = 5 VDC
VOUT Short to GND, TA = 2 5°C
VOUT Short to VCC, TA = 25°C
2.4
4.5
–3
4.5
6
9
16
Supply Current (Includes Ladder Current)
ICC
ADC0801/02/03/04LCJ/05
fCLK = 640 kHz, VREF/2 = NC,
TA = 25°C and CS = 5 V
1.1
ADC0804LCN/LCWM
1.9
www.ti.com
MAX
114
73
1460
60%
UNITS
µs
1/fCLK
kHz
9708 conv/s
ns
200 ns
200 ns
450 ns
7.5 pF
7.5 pF
15 VDC
0.8 VDC
1 µADC
µADC
3.5 VDC
2.1 VDC
2 VDC
0.4 VDC
VDC
0.4 VDC
0.4 VDC
VDC
VDC
µADC
3 µADC
mADC
mADC
1.8 mA
2.5 mA
(1) Accuracy is specified at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle
limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
(2) With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the
conversion process. The start request is internally latched, see Figure 48 and FUNCTIONAL DESCRIPTION.
(3) The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide
pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse
(see TIMING DIAGRAMS).
4
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