ADC0803, ADC0804, ADC0805
SNOSBI1B â NOVEMBER 2009 â REVISED FEBRUARY 2013
Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard T2L logic voltage levels. These signals have been
renamed when compared to the standard A/D Start and Output Enable labels. In addition, these inputs are active
low to allow an easy interface to microprocessor control busses. For non-microprocessor based applications, the
CS input (pin 1) can be grounded and the standard A/D Start function is obtained by an active low pulse applied
at the WR input (pin 3) and the Output Enable function is caused by an active low pull at the RD input (pin 2).
Analog Differential Voltage Inputs and Common-Mode Rejection
This A/D has additional applications flexibility due to the analog differential voltage input. The VIN(â) input (pin 7)
can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also
useful in 4 mAâ20 mA current loop conversion. In addition, common-mode noise can be reduced by use of the
The time interval between sampling VIN(+) and VIN(â) is 4-1/2 clock periods. The maximum error voltage due to
this slight time difference between the input voltage samples is given by:
âVe is the error voltage due to sampling delay
VP is the peak value of the common-mode voltage
fcm is the common-mode frequency
As an example, to keep this error to 1/4 LSB (â¼5 mV) when operating with a 60 Hz common-mode frequency,
fcm, and using a 640 kHz A/D clock, fCLK, would allow a peak value of the common-mode voltage, VP, which is
which gives VPâ1.9 V.
The allowed range of analog input voltages usually places more severe restrictions on input common-mode noise
An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making
use of the differential input (see Reference Voltage).
Analog Inputs â Input Current
Due to the internal switching action, displacement currents will flow at the analog inputs. This is due to on-chip
stray capacitance to ground as shown in Figure 49.
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