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74ALVC08D View Datasheet(PDF) - NXP Semiconductors.

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Description
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74ALVC08D
NXP
NXP Semiconductors. NXP
74ALVC08D Datasheet PDF : 14 Pages
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Nexperia
74ALVC08
Quad 2-input AND gate
5.2 Pin description
Table 2. Pin description
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
VCC
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6 Functional description
Table 3. Function table [1]
Input
nA
nB
L
L
L
H
H
L
H
H
[1] H = HIGH voltage level; L = LOW voltage level
Output
nY
L
L
L
H
7 Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max Unit
VCC
supply voltage
VI
input voltage
VO
output voltage
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
none
power-down mode, VCC = 0 V
VI < 0 V
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = -40 °C to +85 °C
[1]
[1] [2]
[2]
[3]
-0.5
-0.5
-0.5
-0.5
-
-
-
-
-100
-65
-
+4.6 V
+4.6 V
VCC + 0.5 V
+4.6 V
-50 mA
±50 mA
±50 mA
100 mA
-
mA
+150 °C
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
74ALVC08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 5 October 2017
© Nexperia B.V. 2017. All rights reserved.
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