|ADC08060CIMT/NOPB||8-Bit, 20 MSPS to 60 MSPS, 1.3 m W/MSPS A/D Converter with Internal Sampleand-Hold|
|ADC08060CIMT/NOPB Datasheet PDF : 28 Pages |
SNAS120H – OCTOBER 2000 – REVISED MARCH 2013
While a single voltage source is recommended for the VA and DR VD supplies of the ADC08060, these supply
pins should be well isolated from each other to prevent any digital noise from being coupled into the analog
portions of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass
capacitors close to the supply pins.
As is the case with all high speed converters, the ADC08060 should be assumed to have little power supply
rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any
system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other
No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300
mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be
sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than
does the voltage at the ADC08060 power pins.
THE DIGITAL INPUT PINS
The ADC08060 has two digital input pins: The PD pin and the Clock pin.
The PD Pin
The Power Down (PD) pin, when high, puts the ADC08060 into a low power mode where power consumption is
reduced to 1 mW. Output data is valid and accurate about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is
The ADC08060 Clock
Although the ADC08060 is tested and its performance is ensured with a 60 MHz clock, it typically will function
well with clock frequencies from 20 MHz to 70 MHz.
Halting the clock will provide nearly as much power saving as raising the PD pin high. Typical power
consumption with a stopped clock is 3 mW, compared to 1 mW when PD is high. The digital outputs will remain
in the same state as they were before the clock was halted.
Once the clock is restored (or the PD pin is brought low), there is a time of about 1 µs before the output data is
valid. However, because of the linear relationship between total power consumption and clock frequency, the
part requires about 1 µs after the clock is restarted or substantially changed in frequency before the part returns
to its specified accuracy.
The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving
a precise duty cycle is difficult, the ADC08060 is designed to maintain performance over a range of duty cycles.
While it is specified and performance is ensured with a 50% clock duty cycle and 60 Msps, ADC08060
performance is typically maintained with clock high and low times of 3.3 ns, corresponding to a clock duty cycle
range of 40% to 50% with a 60 MHz clock. Note that the clock minimum high and low times may not be used
The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line. If
the clock line is longer than
• tr is the clock rise time
• tPD is the propagation rate of the signal along the trace
If the clock source is used to drive more than just the ADD08060, the CLOCK pin should be a.c. terminated with
a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and
the capacitor value is
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: ADC08060
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