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AD2S1210WDSTZRL7 View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD2S1210WDSTZRL7 Datasheet PDF : 36 Pages
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AD2S1210
Parameter
t29
t30
t31
t32
t33
t34
fSCLK
Description
Delay WR/FSYNC rising edge to SDO high-Z
Delay from SAMPLE before WR/FSYNC falling edge
Delay CS falling edge to WR/FSYNC falling edge in normal mode
A0 and A1 setup time before WR/FSYNC falling edge
A0 and A1 hold time after WR/FSYNC falling edge2
In normal mode, A0 = 0, A1 = 0/1
In configuration mode, A0 = 1, A1 = 1
Delay WR/FSYNC rising edge to WR/FSYNC falling edge
Frequency of SCLK input
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
Limit at TMIN, TMAX
15
6 × tCK + 20 ns
2
2
24 × tCK + 5 ns
8 × tCK + 5 ns
10
20
25
15
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MHz
MHz
MHz
1 Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C.
2 A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the
16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles.
Rev. 0 | Page 7 of 36
 

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