AD2S1210ASTZ View Datasheet(PDF) - Analog Devices

Part Name

Description

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AD2S1210ASTZ

Variable Resolution, 10-Bit to 16-Bit R/D Converter with Reference Oscillator

Analog Devices 

AD2S1210

CIRCUIT DYNAMICS

LOOP RESPONSE MODEL

ERROR

(ACCELERATION)

VELOCITY

θIN

–

k1 × k2

c

1 – z–1

1 – az–1

1 – bz–1

c

1 – z–1

θOUT

Sin/Cos LOOKUP

Figure 38. RDC System Response Block Diagram

The RDC is a mixed-signal device that uses two ADCs to digitize

signals from the resolver and a Type II tracking loop to convert

these to digital position and velocity words.

The first gain stage consists of the ADC gain on the sine/cosine

inputs and the gain of the error signal into the first integrator.

The first integrator generates a signal proportional to velocity.

The compensation filter contains a pole and a zero that are used

to provide phase margin and reduce high frequency noise gain.

The second integrator is the same as the first and generates the

position output from the velocity signal. The sin/cos lookup has

unity gain. The values for the k1, k2, a, b, and c parameters are

outlined in Table 28.

The following equations outline the transfer functions of the

individual blocks as shown in Figure 38, which then combine to

form the complete RDC system loop response.

Integrator1 and Integrator2 transfer function

I(z)

=

1

c

−z

−1

(10)

Compensation filter transfer function

C(z)

=

1−

1−

az

bz

−1

−1

(11)

RDC open-loop transfer function

G(z) = k1× k2 × I(z)2 ×C(z)

(12)

Table 28. RDC System Response Parameters

Parameter Description

k1 (nominal) ADC gain

k2

Error gain

a

Compensator zero coefficient

b

Compensator pole coefficient

c

Integrator gain

10-bit resolution

1.8/2.5

6 × 106 × 2π

8187/8192

509/512

1/1,024,000

RDC closed-loop transfer function

H(z) = G(z)

(13)

1 + G(z)

The closed-loop magnitude and phase responses are that of a

second-order low-pass filter (see Figure 11 and Figure 12).

To convert G(z) into the s-plane, an inverse bilinear transforma-

tion is performed by substituting the following equation for z:

2 +s

z

=

t

2

−s

(14)

t

where t is the sampling period (1/4.096 MHz ≈ 244 ns).

Substitution yields the open-loop transfer function, G(s).

G(s)

=

k1× k2(1 − a) × 1 +

a−b

st +

s2

s2t 2

4

1 + s × t(1 + a)

×

1

+

s

×

2(1 −

t(1 +

a)

b)

(15)

2(1 − b)

This transformation produces the best matching at low frequencies

(f < fSAMPLE). At such frequencies (within the closed-loop

bandwidth of the AD2S1210), the transfer function can be

simplified to

G(s)

≅

Ka

s2

× 1 + st1

1 + st2

(16)

where:

t1

=

t(1 +

2(1 −

a)

a)

t2

=

t(1 +

2(1 −

b)

b)

Ka

=

k1 × k2(1 −

a−b

a)

Solving for each value gives t1, t2, and Ka as outlined in Table 29.

12-bit resolution

1.8/2.5

18 × 106 × 2π

4095/4096

4085/4096

1/4,096,000

14-bit resolution

1.8/2.5

82 x 106 × 2π

8191/8192

16,359/16,384

1/16,384,000

16-bit resolution

1.8/2.5

66 × 106 × 2π

32,767/32,768

32,757/32,768

1/65,536,000

Rev. 0 | Page 32 of 36

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