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AD2S1210DSTZ View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD2S1210DSTZ Datasheet PDF : 36 Pages
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AD2S1210
Pin
No.
13
14 to
17
18
20
21 to
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Mnemonic
DB13/SCLK
DB12 to
DB9
VDRIVE
DB8
DB7 to DB0
Description
Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state data output pin controlled by CS and RD. In
serial mode, this pin acts as the serial clock input.
Data Bit 12 to Data Bit 9. Three-state data output pins controlled by CS and RD.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Decouple this pin to DGND. The voltage range on this pin is 2.3 V to 5.25 V and may be different to the voltage range
at AVDD and DVDD but should never exceed either by more than 0.3 V.
Data Bit 8. Three-state data output pin controlled by CS and RD.
Data Bit 7 to Data Bit 0. Three-state data input/output pins controlled by CS, RD, and WR/FSYNC.
A
B
NM
DIR
RESET
LOT
DOS
A1
A0
EXC
EXC
AGND
SIN
SINLO
AVDD
COSLO
COS
REFBYP
REFOUT
RES0
Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the
resolver format input signals applied to the converter are valid.
Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR
output indicates the direction of the input rotation and is high for increasing angular rotation.
Reset. Logic input. The AD2S1210 requires an external reset signal to hold the RESET input low until VDD is within the
specified operating range of 4.75 V to 5.25 V.
Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. Refer to the Loss of
Position Tracking Detection section.
Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine)
exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and
cosine input voltages. DOS is indicated by a logic low on the DOS pin. Refer to the Signal Degradation Detection
section.
Mode Select 1. Logic input. A1 in conjunction with A0 allows the mode of the AD2S1210 to be selected. Refer to the
Configuration of AD2S1210 section.
Mode Select 0. Logic input. A0 in conjunction with A1 allows the mode of the AD2S1210 to be selected. Refer to the
Configuration of AD2S1210 section.
Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its
complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation
frequency register.
Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal
(EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the
excitation frequency register.
Analog Ground. This pin is the ground reference points for analog circuitry on the AD2S1210. Refer all analog input
signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a
system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
Positive Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210. The
AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Negative Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
Positive Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are 10 μF and 0.01 μF.
Voltage Reference Output.
Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the resolution of the AD2S1210 to be
programmed. Refer to the Configuration of AD2S1210 section.
Rev. 0 | Page 10 of 36
 

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