74ALVCH16543 View Datasheet(PDF) - NXP Semiconductors.
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74ALVCH16543 Datasheet PDF : 17 Pages
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74ALVCH16543
16-bit D-type registered transceiver; 3-state
Rev. 3 — 15 December 2017
Product data sheet
1 General description
The 74ALVCH16543 is a dual octal registered transceiver. Each section contains two
sets of D-type latches for temporary storage of the data flow in either direction.
Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are
provided for each register to permit independent control in either direction of the data
flow.
The 74ALVCH16543 contains two sections each consisting of two sets of eight D-type
latches with separate inputs and controls for each set. For data flow from A to B,
for example, the A-to-B enable (nEAB) inputs must be LOW in order to enter
data from nA0 to nA7, or take data from nB0 to nB7, as indicated in the function
table. With nEAB LOW, a LOW signal on the A-to-B latch enable (nLEAB) input
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the
nLEAB signal stores the A data into the latches. With nEAB and nOEAB both LOW,
the 3-state B output buffers are active and display the data present at the output of
the A latches. Similarly, the nEBA, nLEBA and nOEBA signals control the data flow
from B-to-A.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2 Features and benefits
• CMOS low power consumption
• Direct interface with TTL levels
• MULTIBYTE flow-through standard pin-out architecture
• Back-to-back registers for storage
• Output drive capability 50 Ω transmission lines at 85 °C
• All data inputs have bushold
• Low inductance multiple VCC and GND pins for minimize noise and ground bounce
• Current drive ±24 mA at VCC = 3.0 V.
• 3-state non-inverting outputs for bus oriented applications
• Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
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