74AHC125D-T View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

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74AHC125D-T

Quad buffer/line driver; 3-state

NXP Semiconductors. 

74AHC125; 74AHCT125

Quad buffer/line driver; 3-state

Rev. 04 — 11 January 2008

Product data sheet

1. General description

The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC

standard JESD7-A.

The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state

outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH

at nOE causes the outputs to assume a high-impedance OFF-state.

The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active

LOW enable inputs.

2. Features

s Balanced propagation delays

s All inputs have a Schmitt-trigger action

s Inputs accepts voltages higher than VCC

s For 74AHC125 only: operates with CMOS input levels

s For 74AHCT125 only: operates with TTL input levels

s ESD protection:

x HBM JESD22-A114E exceeds 2000 V

x MM JESD22-A115-A exceeds 200 V

x CDM JESD22-C101C exceeds 1000 V

s Multiple package options

s Specified from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

Description

74AHC125D

74AHCT125D

−40 °C to +125 °C SO14

plastic small outline package; 14 leads;

body width 3.9 mm

74AHC125PW −40 °C to +125 °C

74AHCT125PW

TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

74AHC125BQ −40 °C to +125 °C

74AHCT125BQ

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

Version

SOT108-1

SOT402-1

SOT762-1

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