74LV125 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

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74LV125

Quad buffer/line driver; 3-state

NXP Semiconductors. 

74LV125

Quad buffer/line driver; 3-state

Rev. 03 — 7 April 2009

Product data sheet

1. General description

The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible

with 74HC125 and 74HCT125.

The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The

3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE

causes the outputs to assume a high-impedance OFF-state.

2. Features

I Wide operating voltage: 1.0 V to 5.5 V

I Optimized for low voltage applications: 1.0 V to 3.6 V

I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C

I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and

Tamb = 25 °C

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I Multiple package options

I Specified from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

74LV125N

−40 °C to +125 °C DIP14

74LV125D

−40 °C to +125 °C SO14

74LV125DB

−40 °C to +125 °C SSOP14

74LV125PW

−40 °C to +125 °C TSSOP14

Description

plastic dual in-line package; 14 leads (300 mil)

plastic small outline package; 14 leads;

body width 3.9 mm

plastic shrink small outline package; 14 leads;

body width 5.3 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

Version

SOT27-1

SOT108-1

SOT337-1

SOT402-1

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