datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

FW82801IRQT28 View Datasheet(PDF) - Intel

Part Name
Description
View to exact match
FW82801IRQT28 Datasheet PDF : 885 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
5.20
5.21
5.22
5.23
5.19.8.3 Device Disconnects ................................................................. 224
5.19.8.4 Effect of Resets on Port-Routing Logic........................................ 224
5.19.9 USB 2.0 Legacy Keyboard Operation ....................................................... 224
5.19.10USB 2.0 Based Debug Port .................................................................... 225
5.19.10.1 Theory of Operation ............................................................... 225
5.19.11USB Pre-Fetch Based Pause ................................................................... 229
5.19.12Function Level Reset Support (FLR) ........................................................ 230
5.19.12.1FLR Steps .............................................................................. 230
SMBus Controller (D31:F3) ............................................................................... 230
5.20.1 Host Controller..................................................................................... 231
5.20.1.1 Command Protocols ................................................................ 231
5.20.2 Bus Arbitration..................................................................................... 235
5.20.3 Bus Timing .......................................................................................... 235
5.20.3.1 Clock Stretching ..................................................................... 235
5.20.3.2 Bus Time Out (Intel® ICH9 as SMBus Master)............................. 235
5.20.4 Interrupts / SMI#................................................................................. 236
5.20.5 SMBALERT# ........................................................................................ 237
5.20.6 SMBus CRC Generation and Checking...................................................... 237
5.20.7 SMBus Slave Interface .......................................................................... 237
5.20.7.1 Format of Slave Write Cycle ..................................................... 238
5.20.7.2 Format of Read Command........................................................ 240
5.20.7.3 Slave Read of RTC Time Bytes .................................................. 242
5.20.7.4 Format of Host Notify Command ............................................... 243
Intel® High Definition Audio Overview ................................................................ 244
5.21.1 Intel® High Definition Audio Docking (Mobile Only) ................................... 244
5.21.1.1 Dock Sequence....................................................................... 244
5.21.1.2 Exiting D3/CRST# when Docked ............................................... 245
5.21.1.3 Cold Boot/Resume from S3 When Docked .................................. 246
5.21.1.4 Undock Sequence ................................................................... 246
5.21.1.5 Interaction Between Dock/Undock and Power Management States. 247
5.21.1.6 Relationship between HDA_DOCK_RST# and HDA_RST# ............. 247
5.21.2 Function Level Reset Support (FLR) ........................................................ 248
5.21.2.1 FLR Steps .............................................................................. 248
Intel® Active Management Technology (Intel® AMT) (Digital Office Only)................ 248
5.22.1 Intel® AMT Features ............................................................................. 249
5.22.2 Intel® AMT Requirements ...................................................................... 249
Serial Peripheral Interface (SPI) ........................................................................ 249
5.23.1 SPI Supported Feature Overview ............................................................ 249
5.23.1.1 Non-Descriptor Mode............................................................... 250
5.23.1.2 Descriptor Mode ..................................................................... 250
5.23.1.3 Device Partitioning .................................................................. 251
5.23.2 Flash Descriptor ................................................................................... 251
5.23.2.1 Descriptor Master Region ......................................................... 253
5.23.3 Flash Access ........................................................................................ 254
5.23.3.1 Direct Access Security ............................................................. 254
5.23.3.2 Register Access Security .......................................................... 254
5.23.4 Serial Flash Device Compatibility Requirements ........................................ 254
5.23.4.1 Intel® ICH9 SPI Based BIOS Requirements ................................ 255
5.23.4.2 Integrated LAN Firmware SPI Flash Requirements ....................... 255
5.23.4.3 Intel® Management Engine Firmware SPI Flash Requirements....... 255
5.23.4.4 Hardware Sequencing Requirements.......................................... 256
5.23.5 Multiple Page Write Usage Model ............................................................ 257
5.23.5.1 Soft Flash Protection ............................................................... 257
5.23.5.2 BIOS Range Write Protection .................................................... 257
5.23.5.3 SMI# Based Global Write Protection .......................................... 258
5.23.6 Flash Device Configurations ................................................................... 258
Intel® I/O Controller Hub 9 (ICH9) Family Datasheet
9
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]