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FW82801IRQT28 View Datasheet(PDF) - Intel

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FW82801IRQT28 Datasheet PDF : 885 Pages
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5.14
5.15
5.16
5.13.9.5 THRMTRIP# Signal .................................................................. 176
5.13.10ALT Access Mode.................................................................................. 177
5.13.10.1Write Only Registers with Read Paths in ALT Access Mode ............ 178
5.13.10.2PIC Reserved Bits ................................................................... 180
5.13.10.3Read Only Registers with Write Paths in ALT Access Mode ............ 180
5.13.11System Power Supplies, Planes, and Signals ............................................ 181
5.13.11.1Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5#
and SLP_M# .......................................................................... 181
5.13.11.2SLP_S4# and Suspend-To-RAM Sequencing ............................... 181
5.13.11.3PWROK Signal ........................................................................ 182
5.13.11.4CPUPWRGD Signal .................................................................. 182
5.13.11.5VRMPWRGD Signal .................................................................. 182
5.13.11.6BATLOW# (Battery Low) (Mobile Only) ...................................... 182
5.13.12Clock Generators.................................................................................. 183
5.13.12.1Clock Control Signals from Intel® ICH9 to Clock
Synthesizer (Mobile Only) ........................................................ 183
5.13.13Legacy Power Management Theory of Operation ....................................... 184
5.13.13.1APM Power Management (Desktop Only) .................................... 184
5.13.13.2Mobile APM Power Management (Mobile Only) ............................ 184
5.13.14Reset Behavior..................................................................................... 184
System Management (D31:F0).......................................................................... 186
5.14.1 Theory of Operation.............................................................................. 186
5.14.1.1 Detecting a System Lockup ...................................................... 186
5.14.1.2 Handling an Intruder ............................................................... 186
5.14.1.3 Detecting Improper Firmware Hub Programming ......................... 187
5.14.1.4 Heartbeat and Event Reporting via SMLink/SMBus....................... 187
5.14.2 TCO Modes .......................................................................................... 187
5.14.2.1 TCO Legacy/Compatible Mode .................................................. 187
5.14.2.2 Advanced TCO Mode ............................................................... 189
General Purpose I/O (D31:F0) .......................................................................... 190
5.15.1 Power Wells......................................................................................... 190
5.15.2 SMI# and SCI Routing .......................................................................... 190
5.15.3 Triggering ........................................................................................... 191
5.15.4 Serial POST Codes Over GPIO ................................................................ 191
5.15.4.1 Theory of operation................................................................. 191
5.15.4.2 Serial Message Format ............................................................ 192
5.15.5 Controller Link GPIOs (Digital Office Only) ............................................... 193
SATA Host Controller (D31:F2, F5) .................................................................... 193
5.16.1 SATA Feature Support........................................................................... 194
5.16.2 Theory of Operation.............................................................................. 195
5.16.2.1 Standard ATA Emulation .......................................................... 195
5.16.2.2 48-Bit LBA Operation............................................................... 195
5.16.3 SATA Swap Bay Support ....................................................................... 195
5.16.4 Hot Plug Operation ............................................................................... 195
5.16.4.1 Low Power Device Presence Detection ....................................... 195
5.16.5 Function Level Reset Support (FLR) ........................................................ 196
5.16.5.1 FLR Steps .............................................................................. 196
5.16.6 Intel® Matrix Storage Technology Configuration (Intel® ICH9R, ICH9DH,
ICH9DO, ICH9M and ICH9M-E Only) ....................................................... 197
5.16.6.1 Intel® Matrix Storage Manager RAID Option ROM........................ 197
5.16.7 Power Management Operation................................................................ 198
5.16.7.1 Power State Mappings ............................................................. 198
5.16.7.2 Power State Transitions ........................................................... 199
5.16.7.3 SMI Trapping (APM) ................................................................ 200
5.16.8 SATA Device Presence........................................................................... 200
5.16.9 SATA LED............................................................................................ 200
Intel® I/O Controller Hub 9 (ICH9) Family Datasheet
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